公开(公告)号：US20150125063A1

公开(公告)日：2015-05-07

申请号：US14071667

申请日：2013-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Hsien Hsieh ,  Ming-Jui Chen ,  Cheng-Te Wang ,  Ping-I Hsieh ,  Jing-Yi Lee

IPC: G06T7/00

CPC classification number: G06T7/0004 ,  G03F1/36 ,  G06K9/00 ,  G06T7/001 ,  G06T2207/30148

Abstract: A calculation method of optical proximity correction includes providing at least a feature pattern to a computer system. At least a first template and a second template are defined so that portions of the feature pattern are located in the first template and the rest of the feature pattern is located in the second template. The first template and the second template have a common boundary. Afterwards, a first calculation zone is defined to overlap an entire first template and portions of the feature pattern out of the first template. Edges of the feature pattern within the first calculation zone are then fragmented from the common boundary towards two ends of the feature pattern so as to generate at least two first beginning segments respectively at two sides of the common boundary. Finally, positions of the first beginning segments are adjusted so as to generate first adjusted segments.

Abstract translation: 光学邻近校正的计算方法包括至少向计算机系统提供特征图案。 定义至少第一模板和第二模板，使得特征图案的部分位于第一模板中，并且特征图案的其余部分位于第二模板中。 第一个模板和第二个模板有一个共同的边界。 之后，定义第一计算区域以将整个第一模板和第一模板中的特征模式的部分重叠。 然后将第一计算区域内的特征图案的边缘从公共边界分割成特征图案的两端，以便分别在公共边界的两侧产生至少两个第一开始段。 最后，调整第一起始段的位置，以产生第一调整段。

公开(公告)号：US20150052491A1

公开(公告)日：2015-02-19

申请号：US13968391

申请日：2013-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.

Abstract translation: 提供了一种用于生成布局图案的方法。 首先，将布局图案提供给计算机系统，并将其分为两个子图案和空白图案。 每个子图案具有简单整数比例的间距，并且空白图案在两个子图案之间。 然后，生成多个第一条纹图案和至少两个第二条纹图案。 第一条形图案的边缘与子图案的边缘对齐，并且第一条纹图案具有相等的间隔和宽度。 第二条纹图案的间距或宽度与第一条纹图案的间距或宽度不同。

公开(公告)号：US08930858B1

公开(公告)日：2015-01-06

申请号：US14091345

申请日：2013-11-27

Applicant: United Microelectronics Corp.

Inventor： Hui-Fang Kuo ,  Ming-Jui Chen

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A smooth process is provided in the present invention. The smooth process is applied to a retarget layout, wherein the retarget layout is dissected into a plurality of segments. Furthermore, the retarget layout comprises a first original pattern, a first adding pattern and a second adding pattern. The smooth process includes changing the second adding pattern to a first smooth pattern. Latter, a second smooth pattern is added to extend from a bottom of the first smooth pattern and a tail portion of the first adding pattern is shrunk to a third smooth pattern. After the smooth process, an optical proximity correction process is applied to the smooth layout to produce an optical proximity correction layout.

Abstract translation: 在本发明中提供了一个平滑的过程。 平滑过程被应用于重定向布局，其中重新定位布局被解剖成多个段。 此外，重定向布局包括第一原始图案，第一添加图案和第二添加图案。 平滑处理包括将第二加法图案改变为第一平滑图案。 较后者，添加第二平滑图案以从第一平滑图案的底部延伸，并且第一添加图案的尾部部分收缩到第三平滑图案。 在平滑处理之后，将光学邻近校正处理应用于平滑布局以产生光学邻近校正布局。

公开(公告)号：US20140258946A1

公开(公告)日：2014-09-11

申请号：US14287079

申请日：2014-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Fang Kuo ,  Ming-Jui Chen ,  Ting-Cheng Tseng ,  Cheng-Te Wang

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G06F17/5081 ,  G03F1/00 ,  G03F1/70 ,  G03F7/20 ,  G03F7/70466

Abstract: A mask set for double exposure process and method of using said mask set. The mask set is provided with a first mask pattern having a first base and a plurality of first teeth and protruding portions, and a second mask pattern having a second base and a plurality of second teeth, wherein the second base may at least partially overlap the first base such that each of the protruding portions at least partially overlaps one of the second teeth.

Abstract translation: 用于双曝光处理的掩模组和使用所述掩模组的方法。 掩模组具有第一掩模图案，其具有第一基底和多个第一齿和突出部分，第二掩模图案具有第二基底和多个第二牙齿，其中第二基底可以至少部分地与 第一基座，使得每个突出部分至少部分地与第二齿中的一个齿重叠。

公开(公告)号：US08745547B1

公开(公告)日：2014-06-03

申请号：US13940096

申请日：2013-07-11

Applicant: United Microelectronics Corp.

Inventor： Shih-Ming Kuo ,  Ming-Jui Chen ,  Te-Hsien Hsieh ,  Cheng-Te Wang ,  Jing-Yi Lee

IPC: G06F17/50

CPC classification number: G03F1/70

Abstract: A method for making a photomask layout is disclosed. A graphic data of a photomask is provided. A first correction step is performed to the graphic data. A first verification step is performed to all of the graphic data which has been subjected to the first correction step, wherein at least one failed pattern not passing the first verification step is found. A second correction step is performed to the at least one failed pattern, so as to obtain at least one modified pattern. A second verification step is performed only to at least one buffer region covering the at least one modified pattern, wherein the buffer region has an area less than a whole area of the photomask. Besides, each of the first correction step, the first verification step, the second correction step and the second verification step is executed by a computer.

Abstract translation: 公开了一种制造光掩模布局的方法。 提供光掩模的图形数据。 对图形数据执行第一校正步骤。 对已经经过第一校正步骤的所有图形数据执行第一验证步骤，其中找到不通过第一验证步骤的至少一个故障模式。 对所述至少一个故障模式执行第二校正步骤，以便获得至少一个修改的模式。 第二验证步骤仅对覆盖至少一个修改图案的至少一个缓冲区域执行，其中缓冲区域具有小于光掩模的整个区域的面积。 此外，第一校正步骤，第一校验步骤，第二校正步骤和第二校验步骤中的每一个由计算机执行。

公开(公告)号：US12278265B2

公开(公告)日：2025-04-15

申请号：US18206617

申请日：2023-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Heng Liu ,  Chia-Wei Huang ,  Hsin-Jen Yu ,  Yung-Feng Cheng ,  Ming-Jui Chen

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78

Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.

公开(公告)号：US11715759B2

公开(公告)日：2023-08-01

申请号：US17118630

申请日：2020-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Heng Liu ,  Chia-Wei Huang ,  Hsin-Jen Yu ,  Yung-Feng Cheng ,  Ming-Jui Chen

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.

公开(公告)号：US10153034B2

公开(公告)日：2018-12-11

申请号：US15448599

申请日：2017-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/11 ,  G11C11/417 ,  G11C11/412

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

公开(公告)号：US09859170B2

公开(公告)日：2018-01-02

申请号：US15434067

申请日：2017-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L21/8238 ,  H01L21/768 ,  H01L27/11 ,  H01L23/535 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

公开(公告)号：US09627036B2

公开(公告)日：2017-04-18

申请号：US14822911

申请日：2015-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: H01L21/28 ,  H01L23/535 ,  H01L27/11 ,  H01L29/66 ,  G11C11/412 ,  H01L27/02

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.