公开(公告)号：US20220367653A1

公开(公告)日：2022-11-17

申请号：US17347614

申请日：2021-06-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, two shallow trench isolation structures are located in the substrate, a first region, a second region and a third region are defined between the two shallow trench isolation structures, the second region is located between the first region and the third region. Two thick oxide layers are respectively located in the first region and the third region and directly contact the two shallow trench isolation structures respectively, and a thin oxide layer is located in the second region, the thickness of the thick oxide layer in the first region is greater than that of the thin oxide layer in the second region.

公开(公告)号：US10276710B1

公开(公告)日：2019-04-30

申请号：US15965267

申请日：2018-04-27

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

Abstract: A high voltage transistor including a substrate is provided, and the substrate has an indent region. A doped region is disposed in the substrate at both sides of the indent region. A shallow trench isolation (STI) structure is disposed in the doped region of the substrate, at a periphery region of the indent region, wherein a portion of a bottom of the STI structure within the indent region has a protruding part down into the substrate. A gate insulating layer is disposed on the substrate at a central region of the indent region other than the STI structure, wherein the gate insulating layer has a protruding portion. A gate structure is disposed on the gate insulating layer and the STI structure within the indent region, covering the protruding portion of the gate insulating layer.

公开(公告)号：US09653460B1

公开(公告)日：2017-05-16

申请号：US15057130

申请日：2016-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L27/088 ,  H01L29/49 ,  H01L27/02 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/45 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/31051 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.

公开(公告)号：US09397084B1

公开(公告)日：2016-07-19

申请号：US14636122

申请日：2015-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Fan-Chi Meng ,  Shan-Shi Huang

IPC: H01L27/02 ,  H01L21/822 ,  H01L23/528 ,  H01L23/50 ,  H01L29/66 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L27/0255 ,  H01L24/11 ,  H01L24/13 ,  H01L24/43 ,  H01L24/45 ,  H01L27/0296 ,  H01L29/66136 ,  H01L29/861 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A structure of ESD protection circuits on a BEOL layer includes a substrate. A plurality of interconnect layers and an inter-level dielectric layer are disposed on the substrate. The inter-level dielectric layer is disposed between the plurality of interconnect layers. The last layer of the interconnect layers comprises an I/O pad, a first pad and a second pad. A first diode and a second diode are disposed on the last layer of the inter-level dielectric layer, wherein the first diode electrically connects to the I/O pad and the first pad and the second diode electrically connects to the I/O pad and the second pad.

Abstract translation: BEOL层上的ESD保护电路的结构包括基板。 多个互连层和层间电介质层设置在基板上。 层间电介质层设置在多个互连层之间。 互连层的最后一层包括I / O焊盘，第一焊盘和第二焊盘。 第一二极管和第二二极管设置在层间电介质层的最后一层上，其中第一二极管电连接到I / O焊盘，第一焊盘和第二二极管电连接到I / O焊盘， 第二垫。

公开(公告)号：US20250133755A1

公开(公告)日：2025-04-24

申请号：US18498049

申请日：2023-10-31

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li

IPC: H01L21/02 ,  H01L21/768

Abstract: Provided are a capacitor device and a manufacturing method thereof. The capacitor device includes a first electrode, a second electrode, an insulating layer, a first dielectric layer, a second dielectric layer, a third electrode and a fourth electrode. The first electrode is disposed on a substrate. The second electrode is disposed on the first electrode. The insulating layer is disposed between the first electrode and the second electrode. The first dielectric layer is disposed on the substrate and covers the first electrode, the second electrode and the insulating layer. The second dielectric layer is disposed on the first dielectric layer. The third electrode and the fourth electrode are disposed in the second dielectric layer and separated from each other. The third electrode is electrically connected to the first electrode, and the fourth electrode is electrically connected to the second electrode.

公开(公告)号：US12279446B2

公开(公告)日：2025-04-15

申请号：US18645366

申请日：2024-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Ruei-Jhe Tsao ,  Che-Hua Chang

IPC: H10D30/66 ,  H10D30/67

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first depressed top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.

公开(公告)号：US20250102922A1

公开(公告)日：2025-03-27

申请号：US18382528

申请日：2023-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Ruei-Jhe Tsao ,  Shan-Shi Huang ,  Wen-Fang Lee ,  Chiu-Te Lee

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/033

Abstract: The invention provides an exposure method of semiconductor patterns, which comprises the following steps: providing a substrate, performing a first exposure step with a first photomask, forming a first pattern in a first region on the substrate, and performing a second exposure step with a second photomask, forming a second pattern in a second region on the substrate, the first pattern and the second pattern are in contact with each other, and at an interface of the first region And the second region, the first pattern and the second pattern are aligned with each other.

公开(公告)号：US12132106B2

公开(公告)日：2024-10-29

申请号：US17688821

申请日：2022-03-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L31/109 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L31/0328 ,  H01L31/072

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/42392

Abstract: A semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor and a second transistor. The substrate includes a high-voltage region and a low-voltage region. The first transistor is disposed on the HV region, and includes a first gate dielectric layer disposed on a first base, and a first gate electrode on the first gate dielectric layer. The first gate dielectric layer includes a composite structure having a first dielectric layer and a second dielectric layer stacked sequentially. The second transistor is disposed on the LV region, and includes a fin shaped structure protruded from a second base on the substrate, and a second gate electrode disposed on the fin shaped structure. The first dielectric layer covers sidewalls of the second gate electrode and a top surface of the first dielectric layer is even with a top surface of the second gate electrode.

公开(公告)号：US20240339534A1

公开(公告)日：2024-10-10

申请号：US18746063

申请日：2024-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Hua Chang ,  Shin-Hung Li ,  Tsung-Yu Yang ,  Ruei-Jhe Tsao

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/66704

Abstract: A semiconductor device includes a semiconductor substrate, a trench, and a gate structure. The trench is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The gate structure includes a gate electrode, a first gate oxide layer, and a second gate oxide layer. A first portion of the gate electrode is disposed in the trench, and a second portion of the gate electrode is disposed outside the trench. The first gate oxide layer is disposed between the gate electrode and the semiconductor substrate. At least a portion of the first gate oxide layer is disposed in the trench. The second gate oxide layer is disposed between the second portion of the gate electrode and the semiconductor substrate in a vertical direction. A thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer.

公开(公告)号：US12057313B2

公开(公告)日：2024-08-06

申请号：US17556972

申请日：2021-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/8258 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02565 ,  H01L21/8258 ,  H01L29/66969 ,  H01L29/7869

Abstract: The present invention provides a semiconductor structure, including a substrate, a thin-film transistor (TFT) on the substrate, wherein the thin-film transistor including a TFT channel layer, a first source and a first drain in the TFT channel layer and a first capping layer on the TFT channel layer. A MOSFET is on the substrate, with a second gate, a second source and a second drain on two sides of the second gate and a second capping layer on the second gate, wherein top surfaces of the second capping layer and the first capping layer are leveled, and a first ILD layer is on the first capping layer and the second capping layer, wherein the first ILD layer and the first capping layer function collectively as a gate dielectric layer for the TFT.