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公开(公告)号：US07479435B1
公开(公告)日：2009-01-20
申请号：US11007565
申请日：2004-12-08
IPC分类号： H01L29/788
CPC分类号： H01L21/26586 , H01L21/2652 , H01L21/823418 , H01L27/088 , H01L29/0847
摘要： A MOS transistor and subsurface collectors can be formed by using a hard mask and precisely varying the implant angle, rotation, dose, and energy. In this case, a particular atomic species can be placed volumetrically in a required location under the hard mask. The dopant can be implanted to form sub-silicon volumes of arbitrary shapes, such as pipes, volumes, hemispheres, and interconnects.
摘要翻译： 可以通过使用硬掩模并精确地改变植入角度，旋转，剂量和能量来形成MOS晶体管和地下收集器。 在这种情况下，特定的原子物质可以体积地放置在硬掩模下的所需位置。 可以将掺杂剂注入以形成任意形状的子硅体积，例如管道，体积，半球和互连。
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32.发明授权Dual direction ESD clamp based on snapback NMOS cell with embedded SCR 有权基于具有嵌入式SCR的快速恢复NMOS单元的双向ESD钳位公开(公告)号：US07394133B1
公开(公告)日：2008-07-01
申请号：US11216774
申请日：2005-08-31
IPC分类号： H01L29/72
CPC分类号： H01L27/0262 , H01L29/0692 , H01L29/7436 , H01L29/87
摘要： In an ESD protection structure, dual direction ESD protection is provided by forming an n-well isolation ring around an NMOS device so that the p-well in which the NMOS drain is formed is isolated from the underlying p-substrate by the n-well isolation ring. By forming the n-well isolation ring the p-n-p-n structure of an embedded SCR for reverse ESD protection is provided. The width of the n-well isolation ring and its spacing from the NMOS drain are adjusted to provide the desired SCR parameters.
摘要翻译： 在ESD保护结构中，通过在NMOS器件周围形成n阱隔离环来提供双向ESD保护，使得形成NMOS漏极的p阱通过n阱与下面的p衬底隔离 隔离环。 通过形成n阱隔离环，提供了用于反向ESD保护的嵌入式SCR的p-n-p-n结构。 调整n阱隔离环的宽度及其与NMOS漏极的间隔，以提供所需的SCR参数。
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33.发明授权Imaging cell that has a long integration period and method of operating the imaging cell 有权成像细胞具有长的积分期和操作成像细胞的方法公开(公告)号：US07218555B2
公开(公告)日：2007-05-15
申请号：US11242094
申请日：2005-10-03
IPC分类号： G11C11/34 , H01L29/788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11531 , H01L27/14603 , H01L27/14609
摘要： The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.
摘要翻译： 成像单元的积分周期或成像单元暴露于光能的时间通过利用单聚电子可编程只读存储器（EPROM）结构捕获光能而大大增加。 光能从EPROM结构的沟道区形成光电子。 光生成的电子然后被加速成具有电离碰撞，其进而导致电子以与通道区域捕获的光子数成正比的速率注入到EPROM结构的浮动栅极上。
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公开(公告)号：US07209503B1
公开(公告)日：2007-04-24
申请号：US10838671
申请日：2004-05-03
IPC分类号： H01S5/00
CPC分类号： H01L27/1446 , H01L27/146
摘要： An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive regions via the photovoltaic effect.
摘要翻译： 集成电路通过将形成为接收电源电压的PMOS晶体管的p +源极区域等导电区域暴露于来自光源的光能来供电。 导电区域用作通过光电效应在导电区域上产生电压的光电二极管。
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公开(公告)号：US07113427B1
公开(公告)日：2006-09-26
申请号：US11076711
申请日：2005-03-09
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L29/7881
摘要： NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.
摘要翻译： 用于存储三个电荷电平的NVM单元：一个擦除和两个编程状态。 该单元包括提供具有平坦区域或第二峰值的形状的栅极电流对栅极电压曲线的晶体管结构。 为了提供这样的结构，一个实施例组合了具有不同阈值电压的两个并联晶体管，另一实施例使用一个具有可变掺杂的晶体管 栅极电流曲线提供两个编程区域。 对第一状态进行编程包括在一个通道上施加电压，使第一个编程区中的栅极电压升高，然后将其向下斜坡。 对第二状态进行编程包括在通道上施加电压，将栅极电压升高到第一编程区并进入第二编程区，然后将其向下斜坡。 可以选择先将电压降低，然后关闭通道上的电压。
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公开(公告)号：US07075341B1
公开(公告)日：2006-07-11
申请号：US10823455
申请日：2004-04-13
IPC分类号： H03B1/00
CPC分类号： H01L27/0266
摘要： A linear time-driver circuit is provided that consumes low space on-chip. The time-driver circuit is based upon the small capacitor charge of the merged region of a 5V tolerant cascaded NMOS device, a single gate device and a zener diode.
摘要翻译： 提供消耗片上低空间的线性时间驱动电路。 时间驱动电路基于5V容限级联NMOS器件，单栅极器件和齐纳二极管的合并区域的小电容器电荷。
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公开(公告)号：US07057174B1
公开(公告)日：2006-06-06
申请号：US10355904
申请日：2003-01-30
IPC分类号： H01L31/00
CPC分类号： H01L31/08
摘要： A photon detector capable of detecting gigahertz frequency optical signals utilizes a layer of photonic material that is formed adjacent to the coil of an inductor. When a pulsed light source is applied to the layer of photonic material, the photonic material generates eddy currents that alter the magnetic flux of the inductor. The signals can then be detected by detecting the change in the magnetic flux.
摘要翻译： 能够检测千兆赫兹光信号的光子检测器利用与电感线圈相邻形成的光子材料层。 当脉冲光源被施加到光子材料层时，光子材料产生改变电感器的磁通量的涡流。 然后可以通过检测磁通量的变化来检测信号。
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38.发明授权Imaging cell with a non-volatile memory that provides a long integration period and method of operating the imaging cell 有权具有非易失性存储器的成像单元，其提供长的积分期和操作成像单元的方法公开(公告)号：US06972995B1
公开(公告)日：2005-12-06
申请号：US10821391
申请日：2004-04-09
CPC分类号： G11C27/005 , G11C16/10
摘要： The image capture period of an imaging cell, or the total time that an imaging cell is exposed to light energy, is substantially increased by utilizing a non-volatile memory (NVM), such as an electrically-erasable, programmable, read-only-memory (EEPROM) structure. The NVM structure stores and integrates charges that are proportional to the absorbed photons over a large number of sequential integration periods.
摘要翻译： 成像单元的图像捕获周期或成像单元暴露于光能的总时间通过利用诸如电可擦除可编程的只读存储器之类的非易失性存储器（NVM）而显着增加， 存储器（EEPROM）结构。 NVM结构在大量的顺序集成周期内存储和积分与吸收的光子成比例的电荷。
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39.发明授权Imaging cell that has a long integration period and method of operating the imaging cell 有权成像细胞具有长的积分期和操作成像细胞的方法公开(公告)号：US06972457B1
公开(公告)日：2005-12-06
申请号：US10821286
申请日：2004-04-09
IPC分类号： H01L21/8247 , H01L27/115 , H01L27/146 , H01L29/76 , H01L29/788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11531 , H01L27/14603 , H01L27/14609
摘要： The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.
摘要翻译： 成像单元的积分周期或成像单元暴露于光能的时间通过利用单聚电子可编程只读存储器（EPROM）结构捕获光能而大大增加。 光能从EPROM结构的沟道区形成光电子。 光生成的电子然后被加速成具有电离碰撞，其进而导致电子以与通道区域捕获的光子数成正比的速率注入到EPROM结构的浮动栅极上。
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40.发明授权LVTSCR ESD protection clamp with dynamically controlled blocking junction 有权LVTSCR ESD保护钳具有动态控制的阻塞结公开(公告)号：US06970335B1
公开(公告)日：2005-11-29
申请号：US10626105
申请日：2003-07-23
CPC分类号： H01L27/0262
摘要： In an SCR-based ESD protection clamp, the voltage overshoot during an ESD event is reduced by separately controlling the voltage pulse to the drain and emitter contacts of the SCR. The voltage pulse to the drain is preferably delayed using a delay circuit such as an RC circuit. This allows double conductivity modulation to be achieved with lower voltage overshoot.
摘要翻译： 在基于SCR的ESD保护钳位中，通过单独控制SCR的漏极和发射极触点的电压脉冲来降低ESD事件期间的电压过冲。 优选地，使用诸如RC电路的延迟电路来延迟到漏极的电压脉冲。 这允许在较低电压过冲时实现双电导率调制。
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