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    Resistive memory apparatus
    31.
    发明授权
    Resistive memory apparatus 有权

    公开(公告)号：US11823738B2

    公开(公告)日：2023-11-21

    申请号：US17541168

    申请日：2021-12-02

    Applicant: Winbond Electronics Corp.

    Inventor： Frederick Chen ,  Hsiu-Han Liao ,  Po-Yen Hsu ,  Chi-Shun Lin

    IPC: G11C11/00 ,  G11C13/00 ,  G11C5/06

    CPC classification number: G11C13/004 ,  G11C5/063 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069

    Abstract: A resistive memory apparatus including bit lines, word lines, a memory array, bypass paths, select circuits, and a switch circuit is provided. The word lines are respectively crossed with the bit lines. The memory array includes memory elements. One end of each of the memory elements is coupled to the corresponding word line, and another end of each of the memory elements is coupled between a first node and a second node on the corresponding bit line. Each of the bypass paths is connected in parallel with the corresponding bit line between the first node point and the second node. Each of the select circuits is coupled to the corresponding bit line and bypass path, and configured to select the coupled bit line or bypass path. The switch circuit is coupled to the word lines, and configured to select one of the word lines.

    RESISTIVE MEMORY APPARATUS
    32.
    发明公开
    RESISTIVE MEMORY APPARATUS 审中-公开

    公开(公告)号：US20230178149A1

    公开(公告)日：2023-06-08

    申请号：US17541168

    申请日：2021-12-02

    Applicant: Winbond Electronics Corp.

    Inventor： Frederick Chen ,  Hsiu-Han Liao ,  Po-Yen Hsu ,  Chi-Shun Lin

    IPC: G11C13/00 ,  G11C5/06

    CPC classification number: G11C13/004 ,  G11C5/063 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069

    Abstract: A resistive memory apparatus including bit lines, word lines, a memory array, bypass paths, select circuits, and a switch circuit is provided. The word lines are respectively crossed with the bit lines. The memory array includes memory elements. One end of each of the memory elements is coupled to the corresponding word line, and another end of each of the memory elements is coupled between a first node and a second node on the corresponding bit line. Each of the bypass paths is connected in parallel with the corresponding bit line between the first node point and the second node. Each of the select circuits is coupled to the corresponding bit line and bypass path, and configured to select the coupled bit line or bypass path. The switch circuit is coupled to the word lines, and configured to select one of the word lines.

    Resistive random access memory
    34.
    发明授权
    Resistive random access memory 有权

    公开(公告)号：US10593877B2

    公开(公告)日：2020-03-17

    申请号：US15949078

    申请日：2018-04-10

    Applicant: Winbond Electronics Corp.

    Inventor： Frederick Chen ,  Ping-Kun Wang ,  Shao-Ching Liao ,  Po-Yen Hsu ,  Yi-Hsiu Chen ,  Ting-Ying Shen ,  Bo-Lun Wu ,  Meng-Hung Lin ,  Chia-Hua Ho ,  Ming-Che Lin

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.

    METHOD OF FABRICATING RESISTIVE MEMORY
    35.
    发明申请
    METHOD OF FABRICATING RESISTIVE MEMORY 审中-公开

    公开(公告)号：US20200083446A1

    公开(公告)日：2020-03-12

    申请号：US16684547

    申请日：2019-11-14

    Applicant: Winbond Electronics Corp.

    Inventor： Po-Yen Hsu ,  Ting-Ying Shen ,  Chia-Hua Ho ,  Chih-Cheng Fu ,  Frederick Chen

    IPC: H01L45/00

    Abstract: Provided is a method of fabricating a resistive memory including forming a first electrode and a second electrode opposite to each other; forming a variable resistance layer between the first electrode and the second electrode; forming an oxygen exchange layer between the variable resistance layer and the second electrode; and forming a protection layer at least covering sidewalls of the oxygen exchange layer.

    Resistive memory and method of fabricating the same
    36.
    发明授权
    Resistive memory and method of fabricating the same 有权

    公开(公告)号：US10522755B2

    公开(公告)日：2019-12-31

    申请号：US15064603

    申请日：2016-03-09

    Applicant: Winbond Electronics Corp.

    Inventor： Po-Yen Hsu ,  Ting-Ying Shen ,  Chia-Hua Ho ,  Chih-Cheng Fu ,  Frederick Chen

    IPC: H01L45/00

    Abstract: Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.

    Resistive random access memory having selector and current limiter structures
    37.
    发明授权
    Resistive random access memory having selector and current limiter structures 有权

    公开(公告)号：US10468458B2

    公开(公告)日：2019-11-05

    申请号：US15151452

    申请日：2016-05-10

    Applicant: Winbond Electronics Corp.

    Inventor： Frederick Chen

    IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

    Abstract: A resistive random access memory includes a memory cell disposed at an intersection point between a first conductive line and a second conductive line. The memory cell includes a selector structure, a first current limiter structure and a resistor structure. The first current limiter structure is disposed between the selector structure and the first conductive line. The resistor structure is disposed between the selector structure and the second conductive line or between the first current limiter structure and the first conductive line.

    THREE-DIMENSIONAL RESISTIVE MEMORY AND METHOD OF FORMING THE SAME
    40.
    发明申请
    THREE-DIMENSIONAL RESISTIVE MEMORY AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20170271402A1

    公开(公告)日：2017-09-21

    申请号：US15075215

    申请日：2016-03-21

    Applicant: Winbond Electronics Corp.

    Inventor： Frederick Chen ,  Chia-Hua Ho

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L27/2436 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/1616

    Abstract: Provided is a three-dimensional resistive memory including a channel pillar, a first gate pillar, a first gate dielectric layer, first and second stacked structures, a variable resistance pillar and an electrode pillar. The channel pillar is on a substrate. The first gate pillar is on the substrate and at a first side of the channel pillar. The first gate dielectric layer is between the channel pillar and the first gate pillar. The first and second stacked structures are on the substrate and respectively at opposite second and third sides of the channel pillar. Each of the first and second stacked structures includes conductive material layers and insulating material layers alternately stacked. The variable resistance pillar is on the substrate and at a side of the first stacked structure opposite to the channel pillar. The electrode pillar is on the substrate and inside of the variable resistance pillar.

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