公开(公告)号：US20110032749A1

公开(公告)日：2011-02-10

申请号：US12903716

申请日：2010-10-13

申请人： Harry Hongyue Liu ,  Haiwen Xi ,  Antoine Khoueir ,  Song Xue

发明人： Harry Hongyue Liu ,  Haiwen Xi ,  Antoine Khoueir ,  Song Xue

IPC分类号： G11C11/34 ,  H01L45/00

CPC分类号： H01L27/24 ,  G11C11/1659 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/75 ,  H01L27/228

摘要： Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.

摘要翻译： 各种实施例涉及一种包括具有布置在NAND块中的非易失性存储器单元的半导体存储器阵列的装置。 每个单元电池包括与开关元件并联连接的电阻感测元件。 电阻感测元件串联连接以形成第一串行路径，并且开关元件串联连接以形成平行于第一串行路径的第二串行路径。 每个电阻感测元件通过具有在所述元件之间基本上垂直延伸的部分的曲折导电路径串联连接到块中的相邻电阻感测元件，以提供对其的操作隔离。

公开(公告)号：US07830693B2

公开(公告)日：2010-11-09

申请号：US12269656

申请日：2008-11-12

申请人： Harry Hongyue Liu ,  Haiwen Xi ,  Antoine Khoueir ,  Song Xue

发明人： Harry Hongyue Liu ,  Haiwen Xi ,  Antoine Khoueir ,  Song Xue

IPC分类号： G11C5/02

CPC分类号： H01L27/24 ,  G11C11/1659 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/75 ,  H01L27/228

摘要： Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.

摘要翻译： 各种实施例涉及一种包括具有布置在NAND块中的非易失性存储器单元的半导体存储器阵列的装置。 每个单元电池包括与开关元件并联连接的电阻感测元件。 电阻感测元件串联连接以形成第一串行路径，并且开关元件串联连接以形成平行于第一串行路径的第二串行路径。 每个电阻感测元件通过具有在所述元件之间基本上垂直延伸的部分的曲折导电路径串联连接到块中的相邻电阻感测元件，以提供对其的操作隔离。

公开(公告)号：US20100054026A1

公开(公告)日：2010-03-04

申请号：US12198416

申请日：2008-08-26

申请人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

发明人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell.

摘要翻译： 存储单元包括电耦合在写位线和写入源线之间的电磁耦合单元和电耦合在读取位线和读取源极线之间的磁性隧道结数据单元的巨磁电阻单元。 通过巨磁电阻单元的写入电流将巨磁阻单元切换到高电阻状态和低电阻状态之间。 磁隧道结数据单元被配置为通过与巨磁阻单元的静磁耦合在高电阻状态和低电阻状态之间切换。 磁隧道结数据单元由通过磁性隧道结数据单元的读取电流读取。

公开(公告)号：US20140071751A1

公开(公告)日：2014-03-13

申请号：US13610433

申请日：2012-09-11

申请人： YoungPil Kim ,  Dadi Setiadi ,  Wei Tian ,  Antoine Khoueir ,  Rodney Virgil Bowman

发明人： YoungPil Kim ,  Dadi Setiadi ,  Wei Tian ,  Antoine Khoueir ,  Rodney Virgil Bowman

IPC分类号： G11C16/16

CPC分类号： G11C16/14 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/16 ,  G11C2013/0073 ,  G11C2211/5646

摘要： Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a soft erasure is performed on a block of memory cells by toggling an erasure status value without otherwise affecting a written state of the cells in the block. The memory cells are subsequently overwritten with a set of data using a write polarity direction determined responsive to the toggled erasure status value.

摘要翻译： 用于管理存储器中的数据的装置和方法，诸如但不限于闪存阵列。 根据一些实施例，通过切换擦除状态值来对存储器单元块执行软擦除，而不影响块中的单元的写入状态。 随后使用响应于切换的擦除状态值确定的写入极性方向用一组数据覆盖存储器单元。

公开(公告)号：US20130256777A1

公开(公告)日：2013-10-03

申请号：US13434994

申请日：2012-03-30

申请人： Antoine Khoueir ,  YoungPil Kim ,  Rodney Virigil Bowman

发明人： Antoine Khoueir ,  YoungPil Kim ,  Rodney Virigil Bowman

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66825 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/7889

摘要： Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.

公开(公告)号：US08400823B2

公开(公告)日：2013-03-19

申请号：US12774016

申请日：2010-05-05

申请人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

发明人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

IPC分类号： G11C11/00

CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

摘要翻译： 存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。 巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。 磁性隧道结数据单元电耦合在读取位线和读取源极线之间。 磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。 写入电流通过巨磁电阻单元，以将巨磁阻单元切换到高电阻状态和低电阻状态之间。 磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

公开(公告)号：US20120153413A1

公开(公告)日：2012-06-21

申请号：US12973536

申请日：2010-12-20

申请人： Haiwen Xi ,  Antoine Khoueir ,  Brian Lee ,  Patrick J. Ryan

发明人： Haiwen Xi ,  Antoine Khoueir ,  Brian Lee ,  Patrick J. Ryan

IPC分类号： H01L29/82 ,  H01L21/02

CPC分类号： H01L43/08 ,  B82Y40/00 ,  G11C11/161 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/329 ,  H01F41/303 ,  H01L43/12

摘要： An apparatus and associated method for a non-volatile memory cell, such as an STRAM cell. In accordance with various embodiments, a magnetic free layer is laterally separated from an antiferromagnetic layer (AFM) by a non-magnetic spacer layer and medially separated from a synthetic antiferromagnetic layer (SAF) by a magnetic tunneling junction. The AFM pins the magnetization of the SAF through contact with a pinning region of the SAF that laterally extends beyond the magnetic tunneling junction.

摘要翻译： 用于非易失性存储器单元（例如STRAM单元）的装置和相关方法。 根据各种实施例，无磁性层通过非磁性间隔层与反铁磁层（AFM）横向分离，并通过磁性隧道结从中间分离的合成反铁磁层（SAF）。 AFM通过与SAF的钉扎区域的接触来引导SAF的磁化，该区域横向延伸超过磁性隧道结。

公开(公告)号：US08154088B1

公开(公告)日：2012-04-10

申请号：US11860245

申请日：2007-09-24

申请人： Antoine Khoueir ,  Subhash Srinivas Pidaparthi ,  Henry Jim Fulford

发明人： Antoine Khoueir ,  Subhash Srinivas Pidaparthi ,  Henry Jim Fulford

IPC分类号： H01L27/088 ,  H01L21/338 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/425

CPC分类号： H01L21/823814 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/6653

摘要： Improved semiconductor topographies and methods are provided herein for reducing the gate induced drain leakage (GIDL) associated with MOS transistors. In particular, a disposable spacer layer is used as an additional mask during implantation of one or more source/drain regions. The physical spacing between the gate and the source/drain regions of a MOS transistor (i.e., the gate/drain overlap) can be varied by varying the thickness of the disposable spacer layer. For example, a larger spacer layer thickness may be used to decrease the gate/drain overlap and reduce the GIDL associated with the MOS transistor. The disposable spacer layer is completely removed after implantation to enable electrical contact between the source/drain regions and subsequently formed source/drain contacts. A method is also provided herein for independently customizing the amount of current leakage associated with two or more MOS transistors.

摘要翻译： 本文提供了改进的半导体拓扑图和方法，用于减少与MOS晶体管相关的栅极感应漏极泄漏（GIDL）。 特别地，在一个或多个源极/漏极区域的注入期间，一次性间隔层被用作附加掩模。 可以通过改变一次性间隔层的厚度来改变MOS晶体管的栅极和源极/漏极区域之间的物理间隔（即，栅极/漏极重叠）。 例如，可以使用更大的间隔层厚度来减小栅极/漏极重叠并且减小与MOS晶体管相关联的GIDL。 一次性间隔层在植入之后被完全去除，以使得源极/漏极区域和随后形成的源极/漏极接触点之间能够电接触。 本文还提供了一种用于独立地定制与两个或多个MOS晶体管相关联的电流泄漏量的方法。

公开(公告)号：US20110090733A1

公开(公告)日：2011-04-21

申请号：US12974679

申请日：2010-12-21

申请人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

发明人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

IPC分类号： G11C11/15

CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

摘要翻译： 存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。 巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。 磁性隧道结数据单元电耦合在读取位线和读取源极线之间。 磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。 写入电流通过巨磁电阻单元，以在高电阻状态和低电阻状态之间切换巨磁电阻单元。 磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

公开(公告)号：US07881098B2

公开(公告)日：2011-02-01

申请号：US12198416

申请日：2008-08-26

申请人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

发明人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

IPC分类号： G11C11/00

CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell.

摘要翻译： 存储单元包括电耦合在写位线和写入源线之间的电磁耦合单元和电耦合在读取位线和读取源极线之间的磁性隧道结数据单元的巨磁电阻单元。 通过巨磁电阻单元的写入电流将巨磁阻单元切换到高电阻状态和低电阻状态之间。 磁隧道结数据单元被配置为通过与巨磁阻单元的静磁耦合在高电阻状态和低电阻状态之间切换。 磁隧道结数据单元由通过磁性隧道结数据单元的读取电流读取。