公开(公告)号：US20070259494A1

公开(公告)日：2007-11-08

申请号：US11780026

申请日：2007-07-19

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L21/8234 ,  H01L21/4763

CPC分类号： H01L28/20 ,  H01L21/76838 ,  H01L27/0629

摘要： Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.

摘要翻译： 形成集成电路器件的方法可以包括在集成电路衬底上形成绝缘层，在绝缘层上形成第一导电层，在第一导电层上形成第二导电层，使第一导电层位于第二导电层之间 导电层和绝缘层。 此外，第一导电层可以是第一材料的层，第二导电层可以是第二材料的层，并且第一和第二材料可以不同。 可以在第二导电层中形成孔，使得第一导电层的一部分通过该孔露出。 在第二导电层中形成孔之后，可以对第一和第二导电层进行图案化，以使第一导电层和第二导电层的围绕通过孔露出的部分的部分被去除，同时保持第一导电层的部分 以前暴露在洞里。

公开(公告)号：US06977197B2

公开(公告)日：2005-12-20

申请号：US10884040

申请日：2004-07-02

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC分类号： H01L28/91 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855

摘要： The present invention discloses a semiconductor device, comprising: bit line landing pads formed over a semiconductor substrate; storage landing pads formed on both sides of the bit line landing pads; a bit line interlayer insulator formed over the whole surface of the semiconductor substrate having the landing pads; a plurality of parallel bit line patterns arranged on the bit line interlayer insulator; bit line insulating layer patterns filling in gate regions between the bit line patterns; upper contact holes formed in the bit line insulating layer patterns to expose side walls of the bit line patterns and located higher than upper surfaces of the bit line patterns; contact hole spacers covering the side walls of the upper contact holes; lower contact holes penetrating the bit line insulating layer patterns and the bit line interlayer insulator below holes surrounded by the contact hole spacers to expose the storage node landing pads and self-alighed with the upper contact holes; and storage node contact plugs filling in the upper and lower contact holes.

摘要翻译： 本发明公开了一种半导体器件，包括：形成在半导体衬底上的位线着色焊盘; 存储着陆垫形成在位线着陆垫的两侧; 形成在具有着色焊盘的半导体衬底的整个表面上的位线层间绝缘体; 布置在位线层间绝缘体上的多个并行位线图案; 填充在位线图案之间的栅极区域中的位线绝缘层图案; 形成在位线绝缘层图案中的上接触孔暴露位线图案的侧壁并且位于比位线图案的上表面高; 覆盖上接触孔的侧壁的接触孔间隔件; 穿过位线绝缘层图案的下接触孔和由接触孔间隔件包围的孔下方的位线层间绝缘体暴露存储节点着陆焊盘并与上接触孔自称; 以及填充上，下接触孔的存储节点接触塞。

公开(公告)号：US06927126B2

公开(公告)日：2005-08-09

申请号：US10830941

申请日：2004-04-22

申请人： Je-Min Park ,  Seung-young Son ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Seung-young Son ,  Yoo-Sang Hwang

IPC分类号： H01L21/28 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8242

CPC分类号： H01L21/76897 ,  H01L21/76831 ,  H01L2924/0002 ,  H01L2924/00

摘要： A second insulating layer is formed on a first insulating layer. A plurality of stacks each including a bit line and a bit line mask are formed on the second insulating layer. A third insulating layer is formed overlying the second insulating layer to fill gaps between the plurality of stacks. A hard mask layer is formed on the third insulating layer. A photoresist pattern is formed on the hard mask layer. The photoresist pattern has an opening region that intersects the plurality of stacks. The hard mask layer and the third insulating layer are sequentially etched, using the photoresist pattern as an etching mask, thereby forming a hard mask pattern and forming a recess in the third insulating layer. The recess exposes a portion of upper sidewalls of the bit line mask. Spacers are formed on the exposed upper sidewalls of the bit line mask.

摘要翻译： 在第一绝缘层上形成第二绝缘层。 在第二绝缘层上形成各自包括位线和位线掩模的堆叠。 在第二绝缘层上形成第三绝缘层以填充多个堆叠之间的间隙。 在第三绝缘层上形成硬掩模层。 在硬掩模层上形成光刻胶图形。 光致抗蚀剂图案具有与多个堆叠相交的开口区域。 使用光致抗蚀剂图案作为蚀刻掩模，依次蚀刻硬掩模层和第三绝缘层，从而形成硬掩模图案并在第三绝缘层中形成凹部。 凹口露出位线掩模的上侧壁的一部分。 间隔件形成在位线掩模的暴露的上侧壁上。

公开(公告)号：US08884340B2

公开(公告)日：2014-11-11

申请号：US13298644

申请日：2011-11-17

申请人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

发明人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

IPC分类号： H01L21/336 ,  H01L29/772 ,  G11C11/404 ,  H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  G11C11/408 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234

CPC分类号： G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

摘要翻译： 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。

公开(公告)号：US20120119286A1

公开(公告)日：2012-05-17

申请号：US13285263

申请日：2011-10-31

申请人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

发明人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/10876 ,  H01L29/1033 ,  H01L29/1087 ,  H01L29/66666 ,  H01L29/7831

摘要： A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect.

摘要翻译： 半导体器件具有在基板上竖直延伸的多个垂直通道，在垂直通道之间延伸的多个位线，分别包括与垂直通道的第一侧相邻设置的多个栅极的多条字线，以及 多个导电元件设置在与第一侧相对的垂直通道的第二侧附近。 导电元件可以提供到已经累积在相关联的垂直通道中的电荷载体的衬底的路径，从而减轻所谓的浮动效应。

公开(公告)号：US20110117715A1

公开(公告)日：2011-05-19

申请号：US13010297

申请日：2011-01-20

申请人： Jong-Seo Hong ,  Jeong-Sic Jeon ,  Chun-Suk Suh ,  Yoo-Sang Hwang

发明人： Jong-Seo Hong ,  Jeong-Sic Jeon ,  Chun-Suk Suh ,  Yoo-Sang Hwang

IPC分类号： H01L21/02

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852

摘要： A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.

摘要翻译： 公开了一种半导体存储器件的电容器及其形成方法。 衬垫层间绝缘层设置在有源区的半导体衬底上。 着陆垫和中央着陆垫分别设置在活动区域​​的周边部分和中心部分中，以穿透垫层间绝缘层。 中央着陆垫的上表面与着陆垫的上表面具有不同的面积。 掩埋层间绝缘层形成在焊盘层间绝缘层上，以覆盖着陆焊盘和中央着陆焊盘。 在相应的着陆焊盘上形成埋入的插塞以穿透埋入的层间绝缘层。 下电极形成在埋地塞上。

公开(公告)号：US20060205141A1

公开(公告)日：2006-09-14

申请号：US11364635

申请日：2006-02-27

申请人： Je-Min Park ,  Yoo-Sang Hwang ,  Seok-Soon Song

发明人： Je-Min Park ,  Yoo-Sang Hwang ,  Seok-Soon Song

IPC分类号： H01L21/8242

CPC分类号： H01L27/10855 ,  H01L27/10817

摘要： A method includes forming a lower dielectric layer on a semiconductor substrate, forming a bit line landing pad and a storage landing pad that penetrate the lower dielectric layer, covering the lower dielectric layer, the bit line landing pad, and the storage landing pad with an intermediate dielectric layer, forming an upper dielectric layer on the intermediate dielectric layer, partially removing the upper dielectric layer and the intermediate dielectric layer to form a contact opening that exposes the storage landing pad and a portion of the lower dielectric layer, forming a contact spacer on an inner wall of the contact opening, and filling the contact opening with a contact plug, a top surface of the contact plug larger than a surface of the contact plug that is in contact with the storage landing pad, the top surface of the contact plug eccentric in relation to the storage landing pad.

摘要翻译： 一种方法包括在半导体衬底上形成下电介质层，形成位线着陆焊盘和穿透下电介质层的存储着陆焊盘，覆盖下电介质层，位线着陆焊盘和存储着陆焊盘 中间介电层，在中间介电层上形成上电介质层，部分地去除上电介质层和中间电介质层，以形成暴露存储着陆焊盘和下电介质层的一部分的接触开口，形成接触间隔物 在接触开口的内壁上，并用接触塞填充接触开口，接触插塞的顶表面大于接触插塞的与储存着陆垫接触的表面，触头顶表面 相对于存储着陆垫插头偏心。

公开(公告)号：US20060113633A1

公开(公告)日：2006-06-01

申请号：US11154922

申请日：2005-06-16

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L29/00

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10894 ,  H01L28/91

摘要： A semiconductor memory device comprises a cell capacitor having a first buried contact connected with a semiconductor substrate of a cell region and a first storage node connected with the first buried contact, and a decoupling capacitor for reducing a coupling noise, having a plurality of second buried contacts formed on a semiconductor substrate portion adjacent in the cell region and extended in parallel with each other and a plurality of second storage nodes connected with the second buried contacts.

摘要翻译： 半导体存储器件包括具有与单元区域的半导体衬底连接的第一埋入触点和与第一埋入触点连接的第一存储节点的单元电容器，以及用于降低耦合噪声的去耦电容器，具有多个第二埋入 形成在与单元区域相邻并且彼此平行延伸的半导体衬底部分上的触点以及与第二埋入触点连接的多个第二存储节点。

公开(公告)号：US20050003646A1

公开(公告)日：2005-01-06

申请号：US10884040

申请日：2004-07-02

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L23/48

CPC分类号： H01L28/91 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855

摘要： A semiconductor device comprises bit line landing pads and storage landing pads disposed on both sides of the bit line landing pads overlying a substrate. A bit line interlayer insulating layer overlies the bit line and storage landing pads. A plurality of bit line patternsare disposed on the bit line interlayer insulating layer. The bit line patterns each include a bit line and a bit line capping layer pattern. Line insulating layer patterns are placed on a top surface of the bit line interlayer insulating layer. Upper contact holes are placed in a region between the bit line patterns and higher than upper surfaces of the bit lines. Contact hole spacers cover the side walls of the upper contact holes. Lower contact holes are self-aligned with the upper contact holes and extend through the line insulating layer patterns and the bit line interlayer insulating layer, thereby exposing the storage node landing pads.

摘要翻译： 半导体器件包括位线着陆焊盘和设置在覆盖衬底的位线着色焊盘的两侧上的存储着陆焊盘。 位线层间绝缘层覆盖位线和存储着陆焊盘。 多个位线图案设置在位线层间绝缘层上。 位线图案各自包括位线和位线覆盖层图案。 线绝缘层图案被放置在位线层间绝缘层的顶表面上。 上接触孔位于位线图案之间的区域中，高于位线的上表面。 接触孔间隔件覆盖上接触孔的侧壁。 下接触孔与上接触孔自对准并延伸穿过线绝缘层图案和位线层间绝缘层，从而暴露存储节点着陆焊盘。

公开(公告)号：US06815300B2

公开(公告)日：2004-11-09

申请号：US10427172

申请日：2003-04-30

申请人： Hong-Sik Jeong ,  Ki-Nam Kim ,  Yoo-Sang Hwang

发明人： Hong-Sik Jeong ,  Ki-Nam Kim ,  Yoo-Sang Hwang

IPC分类号： H01L21336

CPC分类号： H01L27/10873 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： In one embodiment, a plurality of gate structures including gate electrodes and insulating layers covering the gate electrodes are formed on a semiconductor substrate. Impurity ions at a low dose for forming a source/drain region are implanted into the semiconductor substrate, using the gate structures as a mask. First insulating spacers are formed on the sidewalls of the gate structures and second insulating spacers are formed on the first insulating spacers. Thereafter, impurity ions at a high dose are implanted into the semiconductor substrate, using the first and second insulating spacers as a mask. Then, the second insulating spacers are removed. Therefore, contact resistance and characteristics of the transistors can be improved by adjusting an effective channel length and contact areas.

摘要翻译： 在一个实施例中，在半导体衬底上形成包括栅电极和覆盖栅电极的绝缘层的多个栅极结构。 使用栅极结构作为掩模，将用于形成源极/漏极区域的低剂量的杂质离子注入到半导体衬底中。 第一绝缘垫片形成在栅极结构的侧壁上，第二绝缘垫片形成在第一绝缘垫片上。 此后，使用第一和第二绝缘间隔物作为掩模，将高剂量的杂质离子注入到半导体衬底中。 然后，去除第二绝缘间隔物。 因此，可以通过调节有效沟道长度和接触面积来提高晶体管的接触电阻和特性。