公开(公告)号：US5014241A

公开(公告)日：1991-05-07

申请号：US337219

申请日：1989-04-12

申请人： Mikio Asakura ,  Kazuyasu Fujishima ,  Yoshio Matsuda

发明人： Mikio Asakura ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C5/06 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/4099 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C5/025 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/4099 ,  G11C5/063 ,  G11C7/14 ,  G11C7/18

摘要： Each of sense amplifiers is coupled to two bit lines with another bit line being interposed therebetween. Information stored in a memory cell is read out onto one of the two bit lines coupled to each of the sense ampliers, while a reference potential is read out onto the other bit line. Outside of the two bit lines, a reference potential is respectively read out onto other bit lines adjacent to the two bit lines. The information stored in the memory cell is read out onto the other bit line between the two bit lines.

摘要翻译： 读出放大器中的每一个耦合到两个位线，另一个位线插在它们之间。 存储在存储器单元中的信息被读出到耦合到每个读出放大器的两个位线中的一个，同时将参考电位读出到另一个位线上。 在两个位线之外，将参考电位分别读出到与两个位线相邻的其它位线上。 存储在存储单元中的信息被读出到两个位线之间的另一位线上。

公开(公告)号：US4855953A

公开(公告)日：1989-08-08

申请号：US158323

申请日：1988-02-19

申请人： Katsuhiro Tsukamoto ,  Masahiro Shimizu ,  Kazuyasu Fujishima ,  Yoshio Matsuda

发明人： Katsuhiro Tsukamoto ,  Masahiro Shimizu ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC分类号： G11C11/404 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/417

CPC分类号： H01L27/10861 ,  G11C11/404 ,  H01L27/10829 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/66181

摘要： A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner surface of a trench formed in a P type silicon substrate, a first capacitor dielectric film formed on the P.sup.+ region and a common electrode layer serving as a memory terminal formed on the first capacitor dielectric film, and a second memory capacitor including the common electrode layer, a second capacitor dielectric film formed on the common electrode layer and a cell plate electrode formed on the second capacitor dielectric film. The memory terminal and a drain region of the access transistor are connected in a self-aligning manner by an electrode having a sidewall shape which is in contact with an end of the memory terminal. Thus, a contact hole need not be formed in the first capacitor dielectric film, so that decrease of the electrical reliability of the first capacitor dielectric film can be prevented. The drain region of the access transistor may be formed by self-alignment with the contact portion of the common electrode layer.

摘要翻译： 动态RAM包括存储器单元的阵列，每个存储器单元包括单个存取晶体管和电荷存储区域。 电荷存储区域包括第一电容器存储器，其包括形成在形成于P型硅衬底中的沟槽的内表面中的用作相对电极的P +区，形成在P +区上的第一电容器电介质膜和用于 作为形成在第一电容器电介质膜上的存储器端子，以及包括公共电极层的第二存储电容器，形成在公共电极层上的第二电容器电介质膜和形成在第二电容器电介质膜上的单元板电极。 存取晶体管的存储器端子和漏极区域通过具有与存储器端子的端部接触的侧壁形状的电极以自对准的方式连接。 因此，不需要在第一电容器电介质膜中形成接触孔，从而可以防止第一电容器电介质膜的电可靠性的降低。 存取晶体管的漏极区可以通过与公共电极层的接触部分进行自对准而形成。

公开(公告)号：US5461589A

公开(公告)日：1995-10-24

申请号：US145733

申请日：1993-11-04

申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC分类号： G11C5/06 ,  G11C7/18 ,  G11C7/02

CPC分类号： G11C5/063 ,  G11C7/18

摘要： A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

摘要翻译： 一种折叠位线结构的半导体存储器件，其在位线对中的每一个的至少一部分中具有交叉部分，使得与相邻位线对的耦合电容值相对于成对位线彼此相等。 优选地，各位线对被等分成4N，并且在分割点处提供交叉部分，使得在相同分割点处具有交叉部分的位线对被布置在交替的位线对上。 优选地，十字部分设置在用于形成恢复电路或感测放大器的区域中。 更优选地，通过所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。

公开(公告)号：US5280443A

公开(公告)日：1994-01-18

申请号：US028906

申请日：1993-03-08

申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC分类号： G11C5/06 ,  G11C7/18

CPC分类号： G11C5/063 ,  G11C7/18

摘要： A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines. Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers. More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

摘要翻译： 一种折叠位线结构的半导体存储器件，其在位线对中的每一个的至少一部分中具有交叉部分，使得与相邻位线对的耦合电容值相对于成对位线彼此相等。 优选地，各位线对被等分成4N，并且在分割点处提供交叉部分，使得在相同分割点处具有交叉部分的位线对被布置在交替的位线对上。 优选地，十字部分设置在用于形成恢复电路或感测放大器的区域中。 更优选地，通过所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。

公开(公告)号：US5250458A

公开(公告)日：1993-10-05

申请号：US793971

申请日：1991-11-18

申请人： Katsuhiro Tsukamoto ,  Masahiro Shimizu ,  Kazuyasu Fujishima ,  Yoshio Matsuda

发明人： Katsuhiro Tsukamoto ,  Masahiro Shimizu ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC分类号： G11C11/404 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78 ,  H01L29/92

CPC分类号： H01L27/10861 ,  G11C11/404 ,  H01L27/10829 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/66181

摘要： A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner surface of a trench formed in a P type silicon substrate, a first capacitor dielectric film formed on the P.sup.+ region and a common electrode layer serving as a memory terminal formed on the first capacitor dielectric film, and a second memory capacitor including the common electrode layer, a second capacitor dielectric film formed on the common electrode layer and a cell plate electrode formed on the second capacitor dielectric film. The memory terminal and a drain region of the access transistor are connected in a self-aligning manner by an electrode having a sidewall shape which is in contact with an end of the memory terminal. Thus, a contact hole need not be formed in the first capacitor dielectric film, so that decrease of the electrical reliability of the first capacitor dielectric film can be prevented. The drain region of the access transistor may be formed by self-alignment with the contact portion of the common electrode layer.

摘要翻译： 动态RAM包括存储器单元的阵列，每个存储器单元包括单个存取晶体管和电荷存储区域。 电荷存储区域包括第一电容器存储器，其包括形成在形成于P型硅衬底中的沟槽的内表面中的用作相对电极的P +区，形成在P +区上的第一电容器电介质膜和用于 作为形成在第一电容器电介质膜上的存储器端子，以及包括公共电极层的第二存储电容器，形成在公共电极层上的第二电容器电介质膜和形成在第二电容器电介质膜上的单元板电极。 存取晶体管的存储器端子和漏极区域通过具有与存储器端子的端部接触的侧壁形状的电极以自对准的方式连接。 因此，不需要在第一电容器电介质膜中形成接触孔，从而可以防止第一电容器电介质膜的电可靠性的降低。 存取晶体管的漏极区可以通过与公共电极层的接触部分进行自对准而形成。

公开(公告)号：US5030586A

公开(公告)日：1991-07-09

申请号：US282803

申请日：1988-12-12

申请人： Yoshio Matsuda ,  Kazuyasu Fujishima

发明人： Yoshio Matsuda ,  Kazuyasu Fujishima

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/1085 ,  H01L27/10805

摘要： In the semiconductor memory device according to the present invention, a n type drain diffused region (9a) to be connected to a bit line (12) is formed on a p type semiconductor substrate (1) and a n type source diffused region (9b) is formed with a prescribed spacing from the n type drain region (9a). On the p type silicon substrate (1), a p type diffused region (16a) of high impurity density and p type diffused region (16b) of high impurity density are formed in such a manner that they are in contact with the n type drain diffused region (9a) and the n type source diffused region (9b), respectively, but not in the channel region of the n channel MOS transistor (18). Consequently, the .alpha. particle-generated charges can be decreased without changing the threshold voltage of the transfer gate transistor.

公开(公告)号：US5012447A

公开(公告)日：1991-04-30

申请号：US276741

申请日：1988-11-28

申请人： Yoshio Matsuda ,  Kazuyasu Fujishima

发明人： Yoshio Matsuda ,  Kazuyasu Fujishima

IPC分类号： G11C11/401 ,  G11C5/06 ,  G11C11/4097

CPC分类号： G11C5/063 ,  G11C11/4097

摘要： Each of the bit lines constituting each of a plurality of bit line pairs included in a portion of a memory cell array comprises even-numbered intersecting portions. At the intersecting portion, the materials of respective bit lines are different from each other. The bit lines are formed of the same material at portions other than the intersecting portions. The intersecting portions are arranged such that one of the bit lines constituting each bit line pair neighbors one of the bit lines constituting an adjacent one of the bit line pairs for a first length and neighbors the other one of the bit lines constituting the adjacent bit line pair for a second length; and the other one of the bit lines constituting the bit line pair neighbors the one of the bit lines of the adjacent bit line pair for the first length and neighbors the other one of the bit lines of the adjacent bit line pair for the second length.

摘要翻译： 包括在存储单元阵列的一部分中的多个位线对中的每一个的每个位线包括偶数相交部分。 在交叉部分，各位线的材料彼此不同。 位线在相交部分以外的部分由相同的材料形成。 相交部分被布置为使得构成每个位线对的位线之一与构成相邻一个位线对的位线之一第一长度相邻，并且与构成相邻位线的位线中的另一个相邻 配对第二个长度; 并且构成位线对的位线中的另一个与第一长度的相邻位线对的位线之一相邻，并且邻近第二长度的相邻位线对的位线的另一个。

公开(公告)号：US4953164A

公开(公告)日：1990-08-28

申请号：US254233

申请日：1988-10-06

申请人： Mikio Asakura ,  Kazuyasu Fujishima ,  Yoshio Matsuda

发明人： Mikio Asakura ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC分类号： G11C11/413 ,  G06F11/10 ,  G06F12/08 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42

CPC分类号： G06F11/1064 ,  G06F12/0802

摘要： There are provided a first memory cell array and a second memory cell array. The first memory cell array comprises a dynamic RAM and the second memory cell array comprises a static RAM. In addition, the second memory cell array has smaller capacity than that of the first memory cell array. An error correcting circuit, a check bit generating circuit and a register are connected between the first memory cell array and the second memory cell array. Data which is frequently accessed is transferred from the first memory cell array to the second memory cell array and stored therein. Access is made to the second memory cell array. When data which is required is not in the second memory cell array, access is made to the first memory cell array. At the time of transferring data from the first memory cell array to the second memory cell array, errors are corrected by the error correcting circuit. The check bit generating circuit is responsive to data whose error is corrected by the error correcting circuit for generating new check bits.

摘要翻译： 提供了第一存储单元阵列和第二存储单元阵列。 第一存储单元阵列包括动态RAM，第二存储单元阵列包括静态RAM。 此外，第二存储单元阵列具有比第一存储单元阵列小的容量。 纠错电路，校验位产生电路和寄存器连接在第一存储单元阵列和第二存储单元阵列之间。 频繁访问的数据从第一存储单元阵列传送到第二存储单元阵列并存储在其中。 访问第二个存储单元阵列。 当所需的数据不在第二存储单元阵列中时，对第一存储单元阵列进行访问。 在将数据从第一存储单元阵列传送到第二存储单元阵列时，错误校正电路校正错误。 校验位产生电路响应于错误被纠错电路校正的数据，用于产生新的校验位。

公开(公告)号：US4918692A

公开(公告)日：1990-04-17

申请号：US201413

申请日：1988-06-02

申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C11/401 ,  G11C29/04 ,  G11C29/42 ,  H01L27/10

CPC分类号： G06F11/1008 ,  G06F11/1076

摘要： A semiconductor memory device comprises a plurality of memory cell array blocks. An address changing system is provided in each memory cell array block. The same address signal is applied to these address changing systems. Each address changing system comprises a plurality of linking devices. By previously blowing out any of the linking devices in each address changing system, an externally applied address signal is changed with another address signal to be applied to a corresponding memory cell array block.

摘要翻译： 半导体存储器件包括多个存储单元阵列块。 在每个存储单元阵列块中提供地址改变系统。 相同的地址信号被应用于这些地址改变系统。 每个地址改变系统包括多个链接装置。 通过先前吹出每个地址改变系统中的任何链接装置，外部施加的地址信号被改变以应用于相应的存储单元阵列块的另一个地址信号。

公开(公告)号：US4914632A

公开(公告)日：1990-04-03

申请号：US271492

申请日：1988-11-15

申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/804 ,  G11C29/808 ,  G11C29/781

摘要： A plurality of word drivers are provided corresponding to a plurality of word lines. A switch band is provided between the plurality of word drivers and a plurality of row decoders. Each row decoder is connected to four word drivers through the switch band. The state of connection between each of the row decoders and the word driver can be changed by the switch band. A spare row decoder, four word drivers and four spare word lines are provided. Any of the row decoders can be replaced with the spare row decoder. Consequently, four spare word driver and four spare word lines can be selected instead of the four word drivers and four word lines connected to the row decoder.

摘要翻译： 针对多个字线提供多个字驱动器。 在多个字驱动器和多个行解码器之间提供开关带。 每行解码器通过开关带连接到四个字驱动器。 每个行解码器和字驱动器之间的连接状态可以通过开关带来改变。 提供备用行解码器，四个字驱动器和四个备用字线。 任何行解码器都可以用备用行解码器替代。 因此，可以选择四个备用字驱动器和四个备用字线，而不是四个字驱动器和连接到行解码器的四个字线。