公开(公告)号：US20170263303A1

公开(公告)日：2017-09-14

申请号：US15066573

申请日：2016-03-10

申请人： Micron Technology, Inc.

发明人： Richard E. Fackenthal

IPC分类号： G11C11/22

CPC分类号： G11C11/2273 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2293

摘要： A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.

公开(公告)号：US20160005451A1

公开(公告)日：2016-01-07

申请号：US14324048

申请日：2014-07-03

申请人： Texas Instruments Incorporated

发明人： Saim Ahmad Qidwai ,  Stephen Keith Heinrich-Barna ,  William Francis Kraus

IPC分类号： G11C11/22

CPC分类号： G11C11/221 ,  G11C5/06 ,  G11C11/22 ,  G11C11/2253 ,  G11C11/2257 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/5657 ,  G11C13/004

摘要： A system on chip (SoC) may have an array ferroelectric bit cells. The array may include a plurality of bit cells organized into a plurality of rows and columns. A set of word lines is configured such that one of the plurality of word lines is connected to each bit cell in a row of bit cells. A set of column oriented platelines is provided, wherein each column of bit cells has one of the plurality of platelines connected to each bit cell in the column of bit cells. A set of bitlines is provided, wherein each column of bit cells has one of the plurality of bitlines connected to each bit cell in the column of bit cells. Multiplexors may be used to allow one plateline drivers, bitline drivers, and sense amps to be shared between multiple platelines and bitlines.

摘要翻译： 片上系统（SoC）可以具有阵列铁电位单元。 阵列可以包括组织成多个行和列的多个位单元。 一组字线被配置为使得多个字线中的一个字连接到一行位单元中的每个位单元。 提供了一组以列为单位的行列，其中每列位单元具有连接到位单元列中的每个位单元的多个板之一。 提供了一组位线，其中每列位单元具有连接到位单元列中的每个位单元的多个位线之一。 多路复用器可以用于允许一个平台驱动器，位线驱动器和感测放大器在多个板条和位线之间共享。

公开(公告)号：US09171603B1

公开(公告)日：2015-10-27

申请号：US14251136

申请日：2014-04-11

申请人： Palo Alto Research Center Incorporated

发明人： David E. Schwartz

IPC分类号： G11C7/00 ,  G11C11/22 ,  G11C11/16 ,  G11C13/00

CPC分类号： G11C11/2293 ,  G01J1/46 ,  G11C11/1673 ,  G11C11/2253 ,  G11C11/2259 ,  G11C11/2275 ,  G11C13/004 ,  G11C16/08 ,  G11C16/32

摘要： A sensor read/write circuit having a sensor, an integrator, a pulse generator, at least a first and second memory device, and a counter. The sensor senses a parameter and produces a sensor output representative of the sensed parameter. The sensor output is provided to the integrator which produces an integrated output representative of the sensed parameter. The integrated output triggers the pulse generator to produce a pulse which causes the first memory device to be written. The above sequence is repeated whereby a new sensor reading is generated and a second pulse causes the second memory device to be written but only if the first memory device has been substantially completely written, the first memory device has been subsequently disabled and the second memory device has been enabled.

摘要翻译： 具有传感器，积分器，脉冲发生器，至少第一和第二存储器件以及计数器的传感器读/写电路。 传感器感测参数并产生表示感测参数的传感器输出。 传感器输出被提供给积分器，该积分器产生表示感测参数的积分输出。 集成输出触发脉冲发生器产生使第一个存储器件被写入的脉冲。 重复上述顺序，由此产生新的传感器读数，并且第二脉冲使得第二存储器件被写入，但是仅当第一存储器件已被基本上完全写入时，第一存储器件已被随后禁用，并且第二存储器件 已启用

公开(公告)号：US08760907B2

公开(公告)日：2014-06-24

申请号：US12956845

申请日：2010-11-30

申请人： Joseph T. Evans, Jr. ,  Calvin B. Ward

发明人： Joseph T. Evans, Jr. ,  Calvin B. Ward

IPC分类号： G11C11/22

CPC分类号： G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/5657 ,  G11C27/005

摘要： A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.

摘要翻译： 公开了具有多个铁电存储单元的铁电存储器，每个强电介质存储单元包括铁电电容器。 铁电存储器包括读写线和多个铁电存储器单元选择总线，每个铁电存储单元相应的一个选择总线。 每个铁电存储单元包括用于响应于与该铁电存储单元相对应的强电介质存储单元选择总线上的信号而分别将铁电存储单元连接到读取线和写入线的第一和第二栅极。 写入电路使电荷存储在当前连接到写入线的强电介质存储单元的铁电电容器中，电荷具有由具有至少三个状态的数据值确定的值。 读取电路测量存储在当前连接到读取线的铁电存储器单元的铁电电容器中的电荷，以产生与其中一个状态对应的输出值。

公开(公告)号：US20140169060A1

公开(公告)日：2014-06-19

申请号：US13715712

申请日：2012-12-14

申请人： PALO ALTO RESEARCH CENTER INCORPORATED

发明人： David Eric Schwartz

IPC分类号： G11C11/22

CPC分类号： G11C11/221 ,  G11C11/22 ,  G11C11/2293 ,  H03K3/355 ,  H03K19/01714

摘要： A pulse generator circuit with ferroelectric memory element is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively. Optionally, a third thin film transistor may be provided to operate as a pass transistor in response to an enable signal. The elements of the circuit are configured such that a rising pulse on an input node triggers an output pulse on an output node in the manner of a monostable multivibrator. The ferroelectric memory element is coupled to the output node such that a pulse on the output node may change a state of the ferroelectric memory element

摘要翻译： 公开了一种具有铁电存储元件的脉冲发生器电路，其被优化用于印刷，溶液处理的薄膜晶体管处理。 在某些实施例中，电路包括分别作为二极管和电阻器工作的双薄膜晶体管。 可选地，可以提供第三薄膜晶体管以响应于使能信号而作为传输晶体管工作。 电路的元件被配置为使得输入节点上的上升脉冲以单稳态多谐振荡器的方式触发输出节点上的输出脉冲。 铁电存储元件耦合到输出节点，使得输出节点上的脉冲可以改变铁电存储元件的状态

公开(公告)号：US12124942B2

公开(公告)日：2024-10-22

申请号：US17109114

申请日：2020-12-01

申请人： ANAFLASH INC.

发明人： Seung-Hwan Song

IPC分类号： G06N3/063 ,  G06F7/544 ,  G06N3/04 ,  G11C11/22 ,  G11C11/54

CPC分类号： G06N3/063 ,  G06F7/5443 ,  G06N3/04 ,  G11C11/54 ,  G06F2207/4824 ,  G11C11/2293

摘要： A serialized neural network computing unit is disclosed. This computing unit comprises: a bit line; a memory array having a plurality of memory blocks, each memory block have one or more than one memory cells, each cell connected to the bit line; a control circuit configured to: apply a serialized input to the memory cells in a sequence such that outputs of the memory cells are produced in a sequence in response to the serialized input, wherein each of the outputs corresponds to a multiplication of the input and a weight value stored in the memory cell; and set a group of reference current levels, each having a specific current amount, for the control circuit to control the memory cells in generating respective output currents corresponding to the set of reference current levels.

公开(公告)号：US12094512B2

公开(公告)日：2024-09-17

申请号：US17896345

申请日：2022-08-26

申请人： Micron Technology, Inc.

发明人： Angelo Visconti ,  Andrea Locatelli

IPC分类号： G11C11/22

CPC分类号： G11C11/2295 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2293 ,  G11C11/2297

摘要： Systems and methods described herein may enable a memory system to selectively provide a signal boost to a memory cell in response to a change in operating condition, like a change in temperature. The systems and methods may include determining to generate a signal boost for a first duration of time and in response to determining to generate the signal boost, generating the signal boost causing an increase in voltage applied to a signal line coupled to a memory cell. The systems and methods may further include, after the first duration of time, ceasing generation of the signal boost.

公开(公告)号：US12062389B2

公开(公告)日：2024-08-13

申请号：US17323968

申请日：2021-05-18

申请人： Micron Technology, Inc.

发明人： Umberto Di Vincenzo

IPC分类号： G11C11/22

CPC分类号： G11C11/2259 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293

摘要： Methods, systems, and devices for accessing a ferroelectric memory cell are described. In some examples, during a first portion of an access procedure, the voltages of a digit line and word line coupled with the memory cell may be increased while the voltage of a plate coupled with the memory cell is held constant, which may support sensing a logic state stored by the memory cell prior the access procedure, and which may result in a first logic state being written to the memory cell. A voltage of the plate may then be increased, and the digit line may then be coupled with the plate. Because the first logic state was previously written to the memory cell, a target logic state may not need to be subsequently written to the memory cell unless different than the first logic state.

公开(公告)号：US11949419B2

公开(公告)日：2024-04-02

申请号：US18084172

申请日：2022-12-19

申请人： Micron Technology, Inc.

发明人： Maksim Kuzmenka ,  Elena Cabrera Bernal

IPC分类号： H03K5/13 ,  G11C11/22 ,  G11C11/4076 ,  H03F3/45 ,  H03G3/30 ,  H03K5/00

CPC分类号： H03K5/13 ,  G11C11/2293 ,  G11C11/4076 ,  H03F3/45179 ,  H03G3/30 ,  G11C11/221 ,  H03K2005/00019 ,  H03K2005/00208

摘要： Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.

公开(公告)号：US11810608B1

公开(公告)日：2023-11-07

申请号：US18061270

申请日：2022-12-02

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Pratyush Pandey ,  Debo Olaosebikan ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： G11C11/22 ,  G11C11/417 ,  G11C5/10 ,  H10B53/10 ,  H10B53/20

CPC分类号： G11C11/221 ,  G11C5/10 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2293 ,  G11C11/417 ,  H10B53/10 ,  H10B53/20

摘要： A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.