公开(公告)号：US08750023B2

公开(公告)日：2014-06-10

申请号：US13230122

申请日：2011-09-12

申请人： Kazuma Furutani ,  Yutaka Shionoiri

发明人： Kazuma Furutani ,  Yutaka Shionoiri

IPC分类号： G11C11/24

CPC分类号： G11C16/02 ,  G11C11/404 ,  G11C11/405 ,  G11C2207/2236

摘要： An object is to provide a semiconductor memory device capable of copying memory data without using an external circuit. The semiconductor memory device includes a bit line to which first terminals of a plurality of memory cells are connected in common; a pre-charge circuit which is connected to the bit line and pre-charges the bit line with a specific potential in data reading; a data holding circuit comprising a capacitor which temporarily holds data read out from the memory cell or data which is written to the memory cell; and an inverted data output circuit which outputs inverted data of data held in the data holding circuit to the bit line. The inverted data output circuit includes a means for controlling output of inverted data of data held in the data holding circuit.

摘要翻译： 本发明的目的是提供一种能够在不使用外部电路的情况下复制存储器数据的半导体存储器件。 半导体存储器件包括多个存储器单元的第一端子共同连接的位线; 连接到位线的预充电电路，并在数据读取中对具有特定电位的位线进行预充电; 一种数据保持电路，包括暂时保存从存储单元读出的数据或写入存储单元的数据的电容器; 以及将保持在数据保持电路中的数据的反相数据输出到位线的反相数据输出电路。 反相数据输出电路包括用于控制保持在数据保持电路中的数据的反相数据的输出的装置。

公开(公告)号：US20130191586A1

公开(公告)日：2013-07-25

申请号：US13743783

申请日：2013-01-17

申请人： Samsung Electronics Co., Ltd.

发明人： Sang Jun Yang

IPC分类号： G06F12/06 ,  G11C7/10

CPC分类号： G06F12/0607 ,  G06F13/1626 ,  G06F13/1684 ,  G11C7/1072 ,  G11C2207/2236

摘要： Methods of operating a memory controller include requesting data from each of a plurality of separate memory devices in response to an in-order multi-memory read request and then reading the requested data from the plurality of separate memory devices. The data read from the plurality of separate memory devices is then transmitted to a system bus along with at least one indication signal that identifies a relationship between an ordering of the requested data according to memory device and an ordering of the transmitted data according to memory device.

摘要翻译： 操作存储器控制器的方法包括响应于按顺序的多存储器读取请求从多个分离存储器设备中的每一个请求数据，然后从多个单独的存储器设备读取所请求的数据。 然后将从多个单独的存储器件读出的数据与至少一个指示信号一起发送到系统总线，该至少一个指示信号根据存储器设备识别所请求数据的顺序与根据存储器设备的发送数据的排序之间的关系 。

公开(公告)号：US20120063206A1

公开(公告)日：2012-03-15

申请号：US13230122

申请日：2011-09-12

申请人： Kazuma Furutani ,  Yutaka Shionoiri

发明人： Kazuma Furutani ,  Yutaka Shionoiri

IPC分类号： G11C11/24

CPC分类号： G11C16/02 ,  G11C11/404 ,  G11C11/405 ,  G11C2207/2236

摘要： An object is to provide a semiconductor memory device capable of copying memory data without using an external circuit. The semiconductor memory device includes a bit line to which first terminals of a plurality of memory cells are connected in common; a pre-charge circuit which is connected to the bit line and pre-charges the bit line with a specific potential in data reading; a data holding circuit comprising a capacitor which temporarily holds data read out from the memory cell or data which is written to the memory cell; and an inverted data output circuit which outputs inverted data of data held in the data holding circuit to the bit line. The inverted data output circuit includes a means for controlling output of inverted data of data held in the data holding circuit.

摘要翻译： 本发明的目的是提供一种能够在不使用外部电路的情况下复制存储器数据的半导体存储器件。 半导体存储器件包括多个存储器单元的第一端子共同连接的位线; 连接到位线的预充电电路，并在数据读取中对具有特定电位的位线进行预充电; 一种数据保持电路，包括暂时保存从存储单元读出的数据或写入存储单元的数据的电容器; 以及将保持在数据保持电路中的数据的反相数据输出到位线的反相数据输出电路。 反相数据输出电路包括用于控制保持在数据保持电路中的数据的反相数据的输出的装置。

公开(公告)号：US20100037014A1

公开(公告)日：2010-02-11

申请号：US12515697

申请日：2007-11-21

申请人： Young-Hun Lim ,  Ji-Tae Ha ,  Ho-Jong Park

发明人： Young-Hun Lim ,  Ji-Tae Ha ,  Ho-Jong Park

IPC分类号： G06F12/00 ,  G06F12/16

CPC分类号： G11C7/22 ,  G11C2207/2236

摘要： A memory device with a self-copy function includes a memory cell array having first and second banks, and a memory interface. The memory interface reads data from a memory area of the first bank corresponding to a source address contained in previously set self-copy information and writes the read data to a memory area of the second bank corresponding to a destination address contained in the self-copy information via a self-copy data path when a self-copy signal is activated by an external self-copy start request.

摘要翻译： 具有自复制功能的存储器件包括具有第一和第二存储体的存储单元阵列和存储器接口。 存储器接口从对应于先前设置的自复制信息中包含的源地址的第一存储体的存储区读取数据，并将读取的数据写入对应于包含在自复制中的目的地地址的第二存储体的存储区域 当通过外部自复制开始请求激活自复制信号时，经由自复制数据路径的信息。

公开(公告)号：US07257682B2

公开(公告)日：2007-08-14

申请号：US11473589

申请日：2006-06-22

申请人： Siva Ramakrishnan ,  Ioannis Schoinas

发明人： Siva Ramakrishnan ,  Ioannis Schoinas

IPC分类号： G06F13/16

CPC分类号： G11C8/06 ,  G11C7/22 ,  G11C2207/2236

摘要： In some embodiments, a comparator compares an incoming memory address with a memory address currently being copied by a memory copy operation. A holding buffer holds the incoming address prior to forwarding it to a memory read/write queue if the incoming memory address is the same as the memory address currently being copied by the memory copy operation, forwards the buffered incoming memory address to the read/write queue once the memory copy operation for the memory address currently being copied has finished. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，比较器将进入的存储器地址与存储器复制操作当前正在复制的存储器地址进行比较。 如果进入的存储器地址与存储器复制操作当前正在复制的存储器地址相同，则保持缓冲器将转发地址保存在存储器读/写队列之前，将缓冲的输入存储器地址转发到读/写 对于当前正在复制的存储器地址的内存复制操作已完成，就会排队。 描述和要求保护其他实施例。

公开(公告)号：US07127566B2

公开(公告)日：2006-10-24

申请号：US10741721

申请日：2003-12-18

申请人： Siva Ramakrishnan ,  Ioannis Schoinas

发明人： Siva Ramakrishnan ,  Ioannis Schoinas

IPC分类号： G06F13/16

CPC分类号： G11C8/06 ,  G11C7/22 ,  G11C2207/2236

摘要： In some embodiments, a comparator compares an incoming memory address with a memory address currently being copied by a memory copy operation. A holding buffer holds the incoming address prior to forwarding it to a memory read/write queue if the incoming memory address is the same as the memory address currently being copied by the memory copy operation, forwards the buffered incoming memory address to the read/write queue once the memory copy operation for the memory address currently being copied has finished. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，比较器将进入的存储器地址与存储器复制操作当前正在复制的存储器地址进行比较。 如果进入的存储器地址与存储器复制操作当前正在复制的存储器地址相同，则保持缓冲器将转发地址保存在存储器读/写队列之前，将缓冲的输入存储器地址转发到读/写 对于当前正在复制的存储器地址的内存复制操作已完成，就会排队。 描述和要求保护其他实施例。

公开(公告)号：US20050135176A1

公开(公告)日：2005-06-23

申请号：US10741721

申请日：2003-12-18

申请人： Siva Ramakrishnan ,  Ioannis Schoinas

发明人： Siva Ramakrishnan ,  Ioannis Schoinas

IPC分类号： G11C7/22 ,  G11C8/00 ,  G11C8/06

CPC分类号： G11C8/06 ,  G11C7/22 ,  G11C2207/2236

摘要： In some embodiments, a comparator compares an incoming memory address with a memory address currently being copied by a memory copy operation. A holding buffer holds the incoming address prior to forwarding it to a memory read/write queue if the incoming memory address is the same as the memory address currently being copied by the memory copy operation, forwards the buffered incoming memory address to the read/write queue once the memory copy operation for the memory address currently being copied has finished. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，比较器将进入的存储器地址与存储器复制操作当前正在复制的存储器地址进行比较。 如果进入的存储器地址与存储器复制操作当前正在复制的存储器地址相同，则保持缓冲器将转发地址保存在存储器读/写队列之前，将缓冲的输入存储器地址转发到读/写 对于当前正在复制的存储器地址的内存复制操作已完成，就会排队。 描述和要求保护其他实施例。

公开(公告)号：US12020764B2

公开(公告)日：2024-06-25

申请号：US17735889

申请日：2022-05-03

申请人： SK hynix Inc.

发明人： Hyung-Sik Won ,  Hyungsup Kim

IPC分类号： G11C8/00 ,  G11C13/00 ,  G11C16/30 ,  G11C16/34 ,  G11C29/00 ,  G11C29/44 ,  G11C29/52 ,  G11C29/04

CPC分类号： G11C29/783 ,  G11C13/0097 ,  G11C16/30 ,  G11C16/349 ,  G11C29/44 ,  G11C29/52 ,  G11C29/76 ,  G11C29/785 ,  G11C29/835 ,  G11C2029/0411 ,  G11C2207/2236

摘要： A memory system includes a plurality of memory devices and a controller. Each of the memory devices includes a memory cell array, a sense amplifier for amplifying data stored in the memory cell array, a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier, a switch coupled to the first memory cell sub-array, and a second memory cell sub-array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the memory device operates as a normal mode, and when the switch is disabled, the memory device operates as a fast mode faster than the normal mode. The controller dynamically sets a mode of each of the memory devices based on requests externally provided, by controlling the switch of each of the memory devices.

公开(公告)号：US11901032B2

公开(公告)日：2024-02-13

申请号：US17735860

申请日：2022-05-03

申请人： SK hynix Inc.

发明人： Hyung-Sik Won ,  Hyungsup Kim

IPC分类号： G11C8/00 ,  G11C29/00 ,  G11C29/44 ,  G11C16/34 ,  G11C13/00 ,  G11C29/52 ,  G11C16/30 ,  G11C29/04

CPC分类号： G11C29/783 ,  G11C13/0097 ,  G11C16/30 ,  G11C16/349 ,  G11C29/44 ,  G11C29/52 ,  G11C29/76 ,  G11C29/785 ,  G11C29/835 ,  G11C2029/0411 ,  G11C2207/2236

摘要： A memory system includes a memory device and a memory controller. The memory device includes a memory cell array including normal memory cells and redundancy memory cells suitable for replacing failed memory cell among the normal memory cells, and a device controller for activating reserved memory cells which are included in the redundancy memory cells and not used to replace the failed memory cell. The memory controller controls the memory device, when a first memory cells are accessed more than a threshold access number, to move data stored in the first memory cells to the reserved memory cells and replace the first memory cells with the reserved memory cells.

公开(公告)号：US20230236752A1

公开(公告)日：2023-07-27

申请号：US18125625

申请日：2023-03-23

申请人： Micron Technology, Inc.

发明人： Perry V. Lea ,  Glen E. Hush

IPC分类号： G06F3/06 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G06F3/0647 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0685 ,  G11C7/1072 ,  G11C2207/2236 ,  G11C2207/2245

摘要： The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.