公开(公告)号：US20140054709A1

公开(公告)日：2014-02-27

申请号：US13595832

申请日：2012-08-27

申请人： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

发明人： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

IPC分类号： H01L29/78 ,  H01L27/088

CPC分类号： H01L29/7887 ,  H01L27/11521

摘要： A transistor device includes a pair of source/drain regions having a channel region there-between. A first gate is proximate the channel region. A gate dielectric is between the first gate and the channel region. A second gate is proximate the channel region. A programmable material is between the second gate and the channel region. The programmable material includes at least one of a) a multivalent metal oxide portion and an oxygen-containing dielectric portion, or b) a multivalent metal nitride portion and a nitrogen-containing dielectric portion. Memory cells and arrays of memory cells are disclosed.

摘要翻译： 晶体管器件包括在其之间具有沟道区的一对源/漏区。 第一个门靠近通道区域。 栅介质位于第一栅极和沟道区之间。 第二个门靠近通道区域。 可编程材料位于第二栅极和沟道区域之间。 可编程材料包括a）多价金属氧化物部分和含氧电介质部分中的至少一种，或b）多价金属氮化物部分和含氮介电部分。 公开了存储器单元和存储器单元阵列。

公开(公告)号：US20140043899A1

公开(公告)日：2014-02-13

申请号：US13571153

申请日：2012-08-09

申请人： Ting-Chang Chang ,  Chih-Hao Dai ,  Fu-Yen Jian ,  Wen-Hung Lo ,  Shih-Chieh Chang ,  Ying-Lang Wang

发明人： Ting-Chang Chang ,  Chih-Hao Dai ,  Fu-Yen Jian ,  Wen-Hung Lo ,  Shih-Chieh Chang ,  Ying-Lang Wang

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C11/5621 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/7887 ,  H01L29/7923

摘要： A method for performing a programming operation to a first memory bit and a second memory bit of a device is described. The method includes applying a pulse train voltage to a metal gate of the device and grounding a substrate of the device. By floating/grounding a drain of the device and/or by floating/grounding the source of the device, the first memory and the second memory bit are programmed. The pulse train voltage includes 10 to 1000 pulses. One pulse includes a peak voltage and a base voltage. The peak voltage ranges from 0.5 V to 10 V. A duration of the peak voltage ranges from 1 nanosecond to 1 millisecond. The base voltage is 0 V. A duration of the base voltage ranges from 1 nanosecond to 1 millisecond.

摘要翻译： 描述了用于对设备的第一存储器位和第二存储器位执行编程操作的方法。 该方法包括将脉冲串电压施加到该器件的金属栅极并将器件的衬底接地。 通过浮置/接地设备的漏极和/或通过浮置/接地设备的源，第一存储器和第二存储器位被编程。 脉冲串电压包括10到1000个脉冲。 一个脉冲包括峰值电压和基极电压。 峰值电压范围为0.5V至10V。峰值电压的持续时间范围为1纳秒至1毫秒。 基极电压为0V。基极电压的持续时间范围为1纳秒至1毫秒。

公开(公告)号：US08472249B2

公开(公告)日：2013-06-25

申请号：US13246582

申请日：2011-09-27

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  G11C2211/4016 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

公开(公告)号：US08405139B2

公开(公告)日：2013-03-26

申请号：US13085884

申请日：2011-04-13

申请人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

发明人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

公开(公告)号：US08369161B2

公开(公告)日：2013-02-05

申请号：US13026075

申请日：2011-02-11

申请人： Yukio Hayakawa

发明人： Yukio Hayakawa

IPC分类号： G11C16/02

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7887

摘要： A semiconductor device includes an insulation layer (14) provided on a semiconductor substrate (12), a p-type semiconductor region (16) provided on the insulation layer, an isolation region (18) provided that surrounds the p-type semiconductor region to reach the insulation layer, an n-type source region (20) and an n-type drain region (22) provided on the p-type semiconductor region, a charge storage region (30) provided above the p-type semiconductor region between the n-type source region and the n-type drain region, and an voltage applying portion that applies a different voltage to the p-type semiconductor region while any of programming, erasing and reading a different data of a memory cell that has the charge storage region is being preformed.

摘要翻译： 半导体器件包括设置在半导体衬底（12）上的绝缘层（14），设置在绝缘层上的p型半导体区域（16），设置在p型半导体区域周围的隔离区域（18） 到达绝缘层，设置在p型半导体区域上的n型源极区域（20）和n型漏极区域（22），设置在p型半导体区域之上的p型半导体区域上方的电荷存储区域（30） n型源极区域和n型漏极区域以及对p型半导体区域施加不同电压的电压施加部，同时对具有电荷存储器的存储单元的不同数据的编程，擦除和读取进行任何编程， 区域正在执行。

公开(公告)号：US08362544B2

公开(公告)日：2013-01-29

申请号：US13222586

申请日：2011-08-31

申请人： Toshiyuki Okayasu

发明人： Toshiyuki Okayasu

IPC分类号： H01L29/788

CPC分类号： H01L27/11519 ,  G01R31/2621 ,  G01R31/319 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7883 ,  H01L29/7887 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a switching device that electrically connects or disconnects a first terminal and a second terminal to/from each other. The switching device includes a semiconductor layer, a drain electrode that is formed in the semiconductor layer, where the drain electrode is connected to the first terminal, a source electrode that is formed in the semiconductor layer, where the source electrode is connected to the second terminal, a gate insulator that is formed on the semiconductor layer between the drain electrode and the source electrode, a floating gate that is formed on the gate insulator, where the floating gate retains a charge therein, and a tunnel gate that is formed on the floating gate, the tunnel gate supplying a tunnel current determined by a driving voltage applied thereto to charge or discharge the floating gate.

摘要翻译： 提供了一种将第一端子和第二端子彼此电连接或断开的开关装置。 开关器件包括半导体层，形成在半导体层中的漏电极，漏电极连接到第一端子，源电极形成在半导体层中，源电极连接到第二端子 端子，形成在漏电极和源电极之间的半导体层上的栅极绝缘体，形成在栅绝缘体上的浮栅，浮栅在其中保持电荷，以及形成在栅电极上的隧道栅， 浮动栅极，隧道栅极提供由施加到其上的驱动电压确定的隧道电流以对浮动栅极进行充电或放电。

公开(公告)号：US08294193B2

公开(公告)日：2012-10-23

申请号：US12915831

申请日：2010-10-29

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： H01L29/788

CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  G11C2211/4016 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory, first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate; the substrate including an isolation layer that isolates the floating substrate region from a portion of the substrate below the isolation layer.

摘要翻译： 具有易失性和非易失性模式和操作方法的半导体存储器。 半导体存储单元包括从衬底延伸的翅片结构，鳍结构包括具有第一导电类型的浮动衬底区域，配置为将数据存储为易失性存储器，与浮置衬底区域接口的第一和第二区域，第一和第 具有第二导电类型的第二区域; 位于浮置衬底区域的相对侧的第一和第二浮栅或俘获层; 位于所述浮置衬底区域和所述浮置栅极或俘获层之间的第一绝缘层，所述浮置栅极或俘获层被配置为接收由所述易失性存储器存储的数据的传送，并将所述数据作为非易失性存储器存储在所述浮置栅极或俘获层中 在中断存储器单元的电源时; 围绕浮动栅极或捕获层和浮置衬底区域的控制栅极; 以及位于所述浮置栅极或俘获层之间的第二绝缘层和所述控制栅极; 所述衬底包括将所述浮置衬底区域与所述隔离层下方的所述衬底的一部分隔离的隔离层。

公开(公告)号：US08241975B2

公开(公告)日：2012-08-14

申请号：US13198507

申请日：2011-08-04

申请人： Jiankang Bu ,  Lee James Jacobson ,  Andre Paul Labonte

发明人： Jiankang Bu ,  Lee James Jacobson ,  Andre Paul Labonte

IPC分类号： H01L21/8238

CPC分类号： H01L29/42332 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

摘要： A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.

摘要翻译： 公开了一种用于提供低电压高密度多位存储闪存的系统和方法。 本发明的双位存储器单元包括具有公共源极，第一漏极和第一沟道以及第二漏极和第二沟道的衬底。 公共控制门位于源的上方。 第一浮栅和第二浮栅位于控制栅的相对侧。 每个浮动栅极形成有与控制栅极相邻的尖锐尖端以及跟随控制栅极表面轮廓的上部曲面。 当存储单元被擦除时，浮动栅极的尖端有效地将电子放电到控制栅极中。 曲面增加了控制栅极和浮栅之间的电容耦合。

公开(公告)号：US08159878B2

公开(公告)日：2012-04-17

申请号：US12915706

申请日：2010-10-29

申请人： Yuniarto Widjaja

发明人： Yuniarto Widjaja

IPC分类号： H01L29/788

CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  G11C2211/4016 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory; first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate; the substrate including an isolation layer that isolates the floating substrate region from a portion of the substrate below the isolation layer.

摘要翻译： 具有易失性和非易失性模式和操作方法的半导体存储器。 半导体存储单元包括从衬底延伸的翅片结构，所述鳍结构包括具有第一导电类型的浮置衬底区域，其被配置为将数据存储为易失性存储器; 第一和第二区域与浮动衬底区域相接合，第一和第二区域中的每一个具有第二导电类型; 位于浮置衬底区域的相对侧的第一和第二浮栅或俘获层; 位于所述浮置衬底区域和所述浮置栅极或俘获层之间的第一绝缘层，所述浮置栅极或俘获层被配置为接收由所述易失性存储器存储的数据的传送，并将所述数据作为非易失性存储器存储在所述浮置栅极或俘获层中 在中断存储器单元的电源时; 围绕浮动栅极或捕获层和浮置衬底区域的控制栅极; 以及位于所述浮置栅极或俘获层之间的第二绝缘层和所述控制栅极; 所述衬底包括将所述浮置衬底区域与所述隔离层下方的所述衬底的一部分隔离的隔离层。

公开(公告)号：US08114732B2

公开(公告)日：2012-02-14

申请号：US12704502

申请日：2010-02-11

申请人： Mieno Fumitake

发明人： Mieno Fumitake

IPC分类号： H01L21/336 ,  H01L21/461 ,  H01L21/8242

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42332 ,  H01L29/7887

摘要： A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of an undercut region underneath the polysilicon gate structure. An aluminum oxide material is formed overlying the polysilicon gate structure filling the undercut region. In a specific embodiment, the aluminum oxide material has a nanocrystalline silicon material sandwiched between a first aluminum oxide layer and a second aluminum oxide layer. The aluminum oxide material is subjected to a selective etching process while maintaining the aluminum oxide material in an insert region in a portion of the undercut region. The method forms a sidewall structure overlying a side region of the polysilicon gate structure.

摘要翻译： 一种用于形成非易失性存储器结构的方法和系统。 该方法包括提供半导体衬底并形成覆盖在半导体衬底的表面区域上的栅极电介质层。 形成覆盖栅极电介质层的多晶硅栅极结构。 该方法使多晶硅栅极结构进入氧化环境，以形成覆盖多晶硅栅极结构的第一氧化硅层和在多晶硅栅极结构下方形成底切区域。 在填充底切区域的多晶硅栅极结构之上形成氧化铝材料。 在具体实施方案中，氧化铝材料具有夹在第一氧化铝层和第二氧化铝层之间的纳米晶硅材料。 对氧化铝材料进行选择性蚀刻处理，同时将氧化铝材料保持在切削区域的一部分中的插入区域中。 该方法形成覆盖多晶硅栅极结构的侧面区域的侧壁结构。