公开(公告)号：US20090251216A1

公开(公告)日：2009-10-08

申请号：US12062539

申请日：2008-04-04

申请人： Dario GIOTTA ,  Richard GAGGL ,  Ivonne DI SANCARLO ,  Andrea BASCHIROTTO

发明人： Dario GIOTTA ,  Richard GAGGL ,  Ivonne DI SANCARLO ,  Andrea BASCHIROTTO

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  H03F3/45179 ,  H03F3/45632 ,  H03F3/45928 ,  H03F2203/45008 ,  H03F2203/45082 ,  H03F2203/45138 ,  H03F2203/45366 ,  H03F2203/45424

摘要： This disclosure relates to a common mode regulation in multi stage differential amplifiers.

摘要翻译： 本公开涉及多级差分放大器中的共模调节。

公开(公告)号：US20090140809A1

公开(公告)日：2009-06-04

申请号：US11949064

申请日：2007-12-03

申请人： Howard H. Chi

发明人： Howard H. Chi

IPC分类号： H03F3/45

CPC分类号： H03F3/45089 ,  H03F2203/45052 ,  H03F2203/45302 ,  H03F2203/45318 ,  H03F2203/45366 ,  H03F2203/45392 ,  H03F2203/45702 ,  H03G1/0023

摘要： A circuit of high performance variable gain amplifier, method of use and design structure on which the subject circuit resides is provided. The circuit comprises a plurality of differential stages having a common input, and output, a common control level input CM and respective individual control level inputs Cx. The circuit also includes a fixed stage that always is biased to an “on” state from the common input.

摘要翻译： 提供了主题电路所在的高性能可变增益放大器，使用方法和设计结构的电路。 电路包括具有公共输入的多个差分级，并且输出公共控制电平输入CM和各个控制电平输入Cx。 该电路还包括一个从公共输入端始终被偏置到“导通”状态的固定级。

公开(公告)号：US20090096490A1

公开(公告)日：2009-04-16

申请号：US11907151

申请日：2007-10-10

申请人： Ming-Ching Kuo ,  Pei-Ling Tsai ,  Chih-Hung Chen

发明人： Ming-Ching Kuo ,  Pei-Ling Tsai ,  Chih-Hung Chen

IPC分类号： H02M11/00

CPC分类号： H03F3/45201 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0043 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45179 ,  H03F2200/451 ,  H03F2203/45292 ,  H03F2203/45318 ,  H03F2203/45322 ,  H03F2203/45366 ,  H03F2203/45394 ,  H03F2203/45544 ,  H03F2203/45638

摘要： A transconductor to convert an input voltage to an output current, includes: a primary transconductance stage to provide the output current from the input voltage and a driving current; an adaptive transconductance stage coupled in series with the primary transconductance stage to generate the driving current from the input voltage; and a bias circuit coupled to provide a primary bias voltage to the primary transconductance stage and an adaptive bias voltage to the adaptive transconductance stage.

摘要翻译： 将输入电压转换为输出电流的跨导体包括：初级跨导级，用于从输入电压和驱动电流提供输出电流; 自适应跨导级与初级跨导级串联耦合以从输入电压产生驱动电流; 以及偏置电路，其耦合以向初级跨导级提供初级偏置电压，并将自适应偏置电压提供给自适应跨导级。

公开(公告)号：US20090027123A1

公开(公告)日：2009-01-29

申请号：US12220430

申请日：2008-07-23

申请人： A. Paul Brokaw

发明人： A. Paul Brokaw

IPC分类号： H03F3/45

CPC分类号： H03F3/45179 ,  H03F2203/45288 ,  H03F2203/45292 ,  H03F2203/45352 ,  H03F2203/45366 ,  H03F2203/45374

摘要： A differential stage which uses a bias generator circuit to set the operating currents of the input stage FETs to make the incremental Gm primarily a function of a single resistor embedded in the biasing circuit, such that the input stage has a Gm which only gradually departs from nominal under overdrive, and continues to supply output currents which increase with an increasing differential input signal.

摘要翻译： 差分级，其使用偏置发生器电路来设置输入级FET的工作电流，以使增量Gm主要是嵌入在偏置电路中的单个电阻器的功能，使得输入级具有仅逐渐离开的Gm 标称值在过驱动下，并继续提供随着差分输入信号增加而增加的输出电流。

公开(公告)号：US07482845B2

公开(公告)日：2009-01-27

申请号：US11469219

申请日：2006-08-31

申请人： Youn Joong Lee ,  Won Tae Choi ,  Chan Woo Park ,  Byung Hoon Kim

发明人： Youn Joong Lee ,  Won Tae Choi ,  Chan Woo Park ,  Byung Hoon Kim

IPC分类号： H03B1/00

CPC分类号： H03F3/45219 ,  H03F3/3022 ,  H03F3/45183 ,  H03F2203/45118 ,  H03F2203/45248 ,  H03F2203/45366 ,  H03F2203/45536 ,  H03F2203/45626

摘要： Provided is an output buffer circuit having a slew rate increasing part configured with a switching element. The output buffer circuit can obtain an output voltage having a high slew rate even though a smaller amount of a bias current than that required in a conventional output buffer is used. Therefore, the output buffer circuit can reduce power consumption. In the output buffer circuit with a compensation capacitive load, an input part has two input terminal receiving differential input voltage signals, and an output part increases a gain of the differential input voltages. A current source biases the output part, and a slew rate increasing part is connected to the output part and the compensation capacitive load. The slew rate increasing part includes a switching element to increase a slew rate of the output buffer circuit.

摘要翻译： 提供一种具有由开关元件构成的压摆率增加部分的输出缓冲器电路。 即使使用比常规输出缓冲器中所需的偏置电流更小的量，输出缓冲器电路也可以获得具有高转换速率的输出电压。 因此，输出缓冲电路可以降低功耗。 在具有补偿容性负载的输出缓冲电路中，输入部分具有两个输入端接收差分输入电压信号，输出部分增加差分输入电压的增益。 电流源偏置输出部分，并且转换速率增加部分连接到输出部分和补偿电容性负载。 压摆率增加部分包括提高输出缓冲电路的转换速率的开关元件。

公开(公告)号：US07450329B2

公开(公告)日：2008-11-11

申请号：US10932240

申请日：2004-09-01

申请人： Jeremy Robert Kuehlwein

发明人： Jeremy Robert Kuehlwein

IPC分类号： G11B5/02

CPC分类号： H03F3/45089 ,  H03F3/45085 ,  H03F2203/45366 ,  H03F2203/45494 ,  H03F2203/45644

摘要： The present invention achieves technical advantages as a preamplifier write driver (10) having a varying common-mode output voltage. This varying common-mode output voltage also adjusts the derivative of the common-mode voltage, which is proportional to the amount of current coupled onto the MR head through parasitic capacitance. Currents of a first circuit (Q0,Q3) and a second circuit (Q1,Q2) are matched to overcome process variations and modeling errors. A pair of transresistance amplifiers (16) are driven by control lines (14) to achieve these matched currents.

摘要翻译： 本发明实现了具有变化的共模输出电压的前置放大器写入驱动器（10）的技术优点。 这种变化的共模输出电压还调节共模电压的导数，其与通过寄生电容耦合到MR头上的电流量成比例。 匹配第一电路（Q 0，Q 3）和第二电路（Q 1，Q 2）的电流以克服工艺变化和建模误差。 一对跨阻放大器（16）由控制线（14）驱动以实现这些匹配电流。

公开(公告)号：US07449949B2

公开(公告)日：2008-11-11

申请号：US11322759

申请日：2005-12-30

申请人： Young Soo Sohn ,  Jung Hwan Choi

发明人： Young Soo Sohn ,  Jung Hwan Choi

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  G11C7/062 ,  G11C7/1051 ,  G11C7/1069 ,  G11C29/026 ,  G11C2207/063 ,  H03F3/45475 ,  H03F3/72 ,  H03F2203/45138 ,  H03F2203/45352 ,  H03F2203/45366 ,  H03F2203/45466 ,  H03F2203/45641 ,  H03F2203/45652 ,  H03F2203/45686

摘要： A data amplifying circuit for an output driver has a swing level that is controllable according to an operation mode. The data amplifying circuit includes a mode responding circuit supplying an additional source current to a source node of an amplifying circuit in response to a mode selection signal. The mode responding circuit controls the supply of the additional source current in accordance with an operation mode. Another data amplifying circuit of a semiconductor device, according to the invention, includes a small-swing amplifier and a full-swing amplifier. The small-swing amplifier causes a swing level of the output signal to be relatively smaller, while the full-swing amplifier causes the output signal swing level be relatively larger. The small-swing and full-swing amplifiers are alternatively enabled in response to the mode selection signal.

摘要翻译： 用于输出驱动器的数据放大电路具有可根据操作模式控制的摆动电平。 数据放大电路包括响应于模式选择信号向放大电路的源节点提供附加源电流的模式响应电路。 模式响应电路根据操作模式控制附加源电流的供应。 根据本发明的半导体器件的另一数据放大电路包括小摆幅放大器和全摆幅放大器。 小摆幅放大器使输出信号的摆幅水平相对较小，而全摆幅放大器使输出信号摆幅水平相对较大。 响应于模式选择信号，可选地使能小摆幅和全摆幅放大器。

公开(公告)号：US20080238545A1

公开(公告)日：2008-10-02

申请号：US11694823

申请日：2007-03-30

申请人： Don Roy Sauer

发明人： Don Roy Sauer

IPC分类号： H03F3/45

CPC分类号： H03F3/45085 ,  H03F1/26 ,  H03F3/4508 ,  H03F3/45596 ,  H03F2200/456 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45366

摘要： A linearized bipolar differential input stage that contains two high gain current mirrors coupled in series with the input voltage signal through the input transistors to allow the output differential current to greatly exceed the DC output current in a Class AB fashion. The extended output current range over and above the DC current significantly lowers the percentage of effects for both DC offset and noise in the output signal path. Non-linearity cancellation is also optimized for the lowest level of input distortion through adjusting transistor area ratios.

摘要翻译： 线性化双极差分输入级，包含两个通过输入晶体管与输入电压信号串联耦合的高增益电流镜，以允许输出差分电流以AB类方式大大超过直流输出电流。 超过直流电流的扩展输出电流范围显着降低了输出信号路径中直流偏移和噪声的影响百分比。 通过调整晶体管面积比，非线性消除也针对最低输入失真水平进行优化。

公开(公告)号：US20080122536A1

公开(公告)日：2008-05-29

申请号：US11903191

申请日：2007-09-20

申请人： Ulrich Theus ,  Juergen Kessel

发明人： Ulrich Theus ,  Juergen Kessel

IPC分类号： H03F3/45

CPC分类号： H03F3/45968 ,  H03F1/486 ,  H03F3/187 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45744 ,  H03F2200/03 ,  H03F2200/36 ,  H03F2203/45138 ,  H03F2203/45212 ,  H03F2203/45241 ,  H03F2203/45366 ,  H03F2203/45632

摘要： The invention relates to an amplifier circuit provided with offset reduction and with a sufficiently high bandwidth, having two input stages of a first amplifier connected in parallel at the input terminals, wherein the first input stage is connected directly to the input terminals, and the second input stage is connected through a second amplifier, and wherein a third amplifier is connected at the output of the first amplifier, wherein the second amplifier is provided with a symmetrical load.

摘要翻译： 本发明涉及一种放大器电路，其具有偏移减小并且具有足够高的带宽，其具有在输入端并联连接的第一放大器的两个输入级，其中第一输入级直接连接到输入端，而第二输入级 输入级通过第二放大器连接，并且其中第三放大器连接在第一放大器的输出处，其中第二放大器设置有对称负载。

公开(公告)号：US07352243B2

公开(公告)日：2008-04-01

申请号：US11148195

申请日：2005-06-09

申请人： Kouichi Nishimura

发明人： Kouichi Nishimura

IPC分类号： H03F3/45

CPC分类号： H03F3/45219 ,  H03F3/45192 ,  H03F2203/45248 ,  H03F2203/45366 ,  H03F2203/45644 ,  H03F2203/45651

摘要： A voltage comparator that realizes high-speed operation with a simple structure includes an input differential stage having a first differential pair and a second differential pair, into which a differential voltage is inputted from differential input terminals In+ and In−, with reverse polarity to each other, folded cascode-type differential stages, which adds a differential output signal of the first differential pair and a differential output signal of the second differential pair and is connected to a differential output of the input differential stage, and oppositely disposed first and second current mirror circuits, which receive differential outputs of the folded cascode-type differential stages into their respective inputs, with reverse polarity to each other and their outputs connected in common to an output terminal. The folded cascode-type differential stage adds the differential output signal of the first differential pair and the differential output signal of the second differential pair.

摘要翻译： 以简单结构实现高速运行的电压比较器包括具有第一差分对和第二差分对的输入差分级，差分电压从差分输入端子In + +和/ 在 ^{- 中，彼此具有相反的极性，折叠共源共栅型差分级，其添加第一差分对的差分输出信号和第二差分对的差分输出信号，并连接到 输入差分级的差分输出和相对布置的第一和第二电流镜电路，其将折叠的共源共栅型差分级的差分输出接收到它们各自的输入中，彼此具有相反的极性，并且它们的输出共同地连接到输出 终奌站。 折叠的共源共栅型差分级将第一差分对的差分输出信号和第二差分对的差分输出信号相加。}