公开(公告)号：US09262269B2

公开(公告)日：2016-02-16

申请号：US14836467

申请日：2015-08-26

申请人： Rambus Inc.

发明人： Yuanlong Wang ,  Frederick A. Ware

IPC分类号： G11C29/00 ,  G06F11/00 ,  G06F11/14 ,  H03M13/29 ,  G06F11/10

CPC分类号： G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

摘要： A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

摘要翻译： 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

公开(公告)号：US09262262B2

公开(公告)日：2016-02-16

申请号：US14853869

申请日：2015-09-14

申请人： Rambus Inc.

发明人： Yuanlong Wang ,  Frederick A. Ware

IPC分类号： H03M13/00 ,  G06F11/10 ,  H03M13/09

CPC分类号： G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

摘要： A controller includes a link interface that is to couple to a first link to communicate bidirectional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

摘要翻译： 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

公开(公告)号：US20150347223A1

公开(公告)日：2015-12-03

申请号：US14823804

申请日：2015-08-11

申请人： Rambus Inc.

发明人： Yuanlong Wang ,  Frederick A. Ware

IPC分类号： G06F11/10 ,  G06F3/06

CPC分类号： G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

摘要： A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

摘要翻译： 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

公开(公告)号：US09195539B2

公开(公告)日：2015-11-24

申请号：US13943755

申请日：2013-07-16

申请人： Silicon Motion Inc.

发明人： Tsung-Chieh Yang ,  Zhen-U Liu

IPC分类号： G11C29/00 ,  G06F11/10 ,  G11B20/18 ,  H03M13/29 ,  H03M13/27

CPC分类号： G06F11/1068 ,  G06F11/1008 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1076 ,  G11B20/1833 ,  H03M13/27 ,  H03M13/29

摘要： A method for reading data from a block of a flash memory is provided, where the block includes a plurality of pages and at least one parity page, each of the pages includes a plurality of sectors used for storing data and associated row parities, each of the sectors of the parity page is used to store a column parity. The method includes: reading data from a specific page of the pages; decoding the data of the specific page; and when a specific sector of the specific page fails to be decoded, sequentially reading all original data of the pages and the parity page, and performing error correction upon the specific sector according to at least a portion of the original data of the pages and the parity page corresponding to the specific sector.

摘要翻译： 提供了一种从闪速存储器块读取数据的方法，其中该块包括多个页面和至少一个奇偶校验页面，每个页面包括用于存储数据和相关行行奇偶校验的多个扇区，每个扇区 奇偶校验页面的扇区用于存储列奇偶校验。 该方法包括：从页面的特定页面读取数据; 解码特定页面的数据; 并且当特定页面的特定扇区不能被解码时，顺序地读取页面和奇偶校验页面的所有原始数据，并且根据页面的原始数据的至少一部分和特定扇区执行错误校正，并且 对应于特定扇区的奇偶校验页。

公开(公告)号：USRE45783E1

公开(公告)日：2015-10-27

申请号：US14320059

申请日：2014-06-30

申请人： LG Electronics Inc.

发明人： Hyoung Gon Lee ,  In Hwan Choi ,  Byoung Gill Kim ,  Won Gyu Song ,  Jong Moon Kim ,  Jin Woo Kim

IPC分类号： H03M13/00 ,  H03M13/27 ,  H03M13/29 ,  H04N21/438 ,  H04N21/2383 ,  H03M13/15

CPC分类号： H03M13/00 ,  H03M13/1515 ,  H03M13/271 ,  H03M13/29 ,  H03M13/2909 ,  H03M13/6538 ,  H04N21/2383 ,  H04N21/4382

摘要： A DTV transmitting system includes a frame encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The frame encoder builds an enhanced data frame and encodes the frame two times for first and second error correction, respectively. It further permutes a plurality of encoded data frames. The randomizer randomizes the permuted enhanced data, and the block processor codes the randomized data at a rate of 1/N1. The group formatter forms a group of enhanced data having one or more data regions and inserts the data coded at the rate of 1/N1 into at least one of the data regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter formats the deinterleaved data into enhanced data packets.

公开(公告)号：US09128858B1

公开(公告)日：2015-09-08

申请号：US13752757

申请日：2013-01-29

申请人： PMC-SIERRA US, INC.

发明人： Rino Micheloni ,  Peter Z. Onufryk ,  Alessia Marelli ,  Christopher I. W. Norrie ,  Ihab Jaser

IPC分类号： G11C29/00 ,  G06F11/10

CPC分类号： G06F11/10 ,  G06F11/1048 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/116 ,  H03M13/1194 ,  H03M13/1197 ,  H03M13/152 ,  H03M13/29 ,  H03M13/353 ,  H03M13/3707 ,  H03M13/3738 ,  H03M13/618

摘要： Apparatuses and methods for correcting errors in data read from memory cells of an integrated circuit device includes an encoder. The encoder is configured from a single parity check matrix and the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero. A decoder is configured from the single parity check matrix and the decoder is configured to be virtually adjustable by setting a log-likelihood ratio (LLR) for a number of bits in the decoder to a strong value. A code-rate that the encoder and decoder uses can be changed by adjusting the number of bits in the encoder that are set to zero and the number of bits in the decoder that are set to the strong LLR value.

摘要翻译： 用于校正从集成电路装置的存储器单元读取的数据中的错误的装置和方法包括编码器。 编码器由单个奇偶校验矩阵配置，并且编码器被配置为通过将编码器中的位数设置为零而实际上可调节。 解码器由单个奇偶校验矩阵配置，并且解码器被配置为通过将解码器中的位数的对数似然比（LLR）设置为强值来实际可调节。 编码器和解码器使用的码率可以通过调整编码器中设置为零的位数和解码器中被设置为强LLR值的位数来改变。

公开(公告)号：US09116826B2

公开(公告)日：2015-08-25

申请号：US13987517

申请日：2013-08-02

申请人： John P Fonseka ,  Eric Morgan Dowling

发明人： John P Fonseka ,  Eric Morgan Dowling

IPC分类号： H03M13/00 ,  G06F11/10

CPC分类号： G06F11/10 ,  G06F11/1048 ,  H03M13/271 ,  H03M13/2742 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2933 ,  H03M13/2939 ,  H03M13/2972 ,  H03M13/3746 ,  H03M13/4115 ,  H03M13/6362

摘要： Serially-concatenated codes are formed in accordance with the present invention using a constrained interleaver. The constrained interleaver cause the minimum distance of the serial concatenated code to increase above the minimum distance of the inner code alone by adding a constraint that forces some or all of the distance of the outer code onto the serially-concatenated code. This allows the serially-concatenated code to be jointly optimized in terms of both minimum distance and error coefficient to provide significant performance advantages. These performance advantages allow a noise margin target to be achieved using simpler component codes and a much shorter interleaver than was needed when using prior art codes such as Turbo codes. Decoders are also provided. Both encoding and decoding complexity can be lowered, and interleavers can be made much shorter, thereby shortening the block lengths needed in receiver elements such as equalizers and other decision-directed loops. Also, other advantages are provided such as the elimination of a error floor present in prior art serially-concatenated codes. That allows the present invention to achieve much higher performance at lower error rates such as are needed in optical communication systems.

公开(公告)号：US20150207629A1

公开(公告)日：2015-07-23

申请号：US14671766

申请日：2015-03-27

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Daisuke OSHIDA ,  Shigeru FURUTA ,  Masayuki HIROKAWA ,  Akira YAMAZAKI ,  Takashi FUJIMORI ,  Shigemasa SHIOTA

IPC分类号： H04L9/32 ,  H03M13/00 ,  H03M13/29

CPC分类号： H04L9/3226 ,  H03M13/29 ,  H03M13/63 ,  H04L9/3278 ,  H04L2209/04 ,  H04L2209/08 ,  H04L2209/34

摘要： A semiconductor device in related art has a problem that security at the time of writing data cannot be sufficiently assured. A semiconductor device of the present invention has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information.

摘要翻译： 相关技术的半导体器件具有无法充分确保写入数据时的安全性的问题。 本发明的半导体器件具有：唯一代码生成单元，其生成初始唯一代码，其是设备唯一的值，并且包括随机位中的错误; 第一纠错单元，校正所述初始唯一码中的错误以产生中间唯一码; 第二纠错单元，修正中间唯一码中的错误，以产生第一确定唯一码; 以及解密单元，利用所述第一确定唯一代码，通过由外部设备通过基于所述中间特征码产生的密钥信息对机密信息进行加密而获得的传输数据进行解密，以生成机密信息。

公开(公告)号：US20150194984A1

公开(公告)日：2015-07-09

申请号：US14590913

申请日：2015-01-06

申请人： Renesas Electronics Corporation

发明人： Yukitoshi TSUBOI ,  Hideo NAGANO

IPC分类号： H03M13/29

CPC分类号： H03M13/2927 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1052 ,  H03M13/095 ,  H03M13/11 ,  H03M13/13 ,  H03M13/1575 ,  H03M13/19 ,  H03M13/29 ,  H03M13/3715 ,  H03M13/6575

摘要： A data processing apparatus including a processor and a memory has a parity/ECC encoder circuit and a parity/ECC decoder circuit. The parity/ECC encoder circuit is disposed in a signal path for writing data to the memory, includes a parity generating circuit for generating a parity of a plurality of bits from data to be written, and writes the generated parity together with the data into the memory. The parity/ECC decoder circuit is disposed in a signal path for reading data from the memory and includes a parity check unit. The parity generating circuit is configured so that each of a plurality of bits configuring the data contributes to generation of a parity of at least two bits. Consequently, the parity check unit can detect a two-bit error at high speed.

摘要翻译： 包括处理器和存储器的数据处理装置具有奇偶校验/ ECC编码器电路和奇偶校验/ ECC解码器电路。 奇偶校验/ ECC编码器电路设置在用于将数据写入存储器的信号路径中，包括奇偶校验生成电路，用于从要写入的数据生成多个比特的奇偶校验，并将生成的奇偶校验与数据一起写入到 记忆。 奇偶校验/ ECC解码器电路设置在用于从存储器读取数据的信号路径中，并且包括奇偶校验单元。 奇偶生成电路被配置为使得构成数据的多个比特中的每一个有助于生成至少两个比特的奇偶校验。 因此，奇偶校验单元可以高速检测两位错误。

公开(公告)号：US20150186207A1

公开(公告)日：2015-07-02

申请号：US14584729

申请日：2014-12-29

申请人： MStar Semiconductor, Inc.

发明人： Tao Zhou

IPC分类号： G06F11/10 ,  H03M13/29 ,  H03M13/09

CPC分类号： G06F11/10 ,  G06F11/1004 ,  G06F11/1435 ,  G06F2201/82 ,  H03M13/05 ,  H03M13/09 ,  H03M13/29 ,  H03M13/35 ,  H03M13/356

摘要： A method for error tracking a log subsystem of a file system is provided. The method includes: when a data block of the log subsystem is recovered to an original position in the file system, calculating a verification code of the data block to obtain a second verification code; determining whether a verification result between the second verification code and a first verification code of the data block stored in a spare space in a submit block of the log subsystem in a disk is consistent; and when the verification result is inconsistent, processing the data block corresponding to the inconsistent verification result. With the above method, given that system performance is least affected, an error and a position of the error of the log subsystem of the file system can be more accurately detected to enhance the reliability of the log subsystem.

摘要翻译： 提供了一种用于错误跟踪文件系统的日志子系统的方法。 该方法包括：当日志子系统的数据块被恢复到文件系统中的原始位置时，计算数据块的验证码以获得第二验证码; 确定存储在盘中的日志子系统的提交块中的备用空间中的第二验证码和数据块的第一验证码之间的验证结果是否一致; 并且当验证结果不一致时，处理与不一致的验证结果相对应的数据块。 利用上述方法，考虑到系统性能影响最小，可以更精确地检测文件系统日志子系统的错误和位置，提高日志子系统的可靠性。