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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    31.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240237331A1

    公开(公告)日：2024-07-11

    申请号：US18350427

    申请日：2023-07-11

    申请人： Samsung Electronics Co., Ltd.

    发明人： Hoin LEE ,  Byung-Hyun LEE ,  Hoouk LEE

    IPC分类号： H10B12/00 ,  H01L29/423

    CPC分类号： H10B12/315 ,  H01L29/42356 ,  H10B12/03 ,  H10B12/482

    摘要： A semiconductor device includes a substrate including a cell array region and a core region disposed around the cell array region; a plurality of storage element contacts; a contact plug; and a contact plug spacer. The plurality of storage element contacts may include a first storage element contact and at least one second storage element contact, the first storage element contact is a closest storage element contact of the plurality of storage element contacts to the core region, such that the first storage element contact is between the core region and the at least one second storage element contact. A step difference in a vertical direction perpendicular to the substrate between a top surface of the first storage element contact and a top surface of the at least one second storage element contact is 5 nm or less.

    Semiconductor memory device and method for forming the same
    32.
    发明授权
    Semiconductor memory device and method for forming the same 有权

    公开(公告)号：US12035519B2

    公开(公告)日：2024-07-09

    申请号：US17673828

    申请日：2022-02-17

    申请人： Fujian Jinhua Integrated Circuit Co., Ltd.

    发明人： Peng Guo ,  Yuanbao Wang

    IPC分类号： H10B12/00 ,  H01L29/06

    CPC分类号： H10B12/30 ,  H01L29/0649 ,  H10B12/482 ,  H10B12/488

    摘要： The present invention discloses a semiconductor memory device and a forming method thereof. The semiconductor memory device includes a substrate, a plurality of bit lines, a strip-shaped isolation structure, a conductive residue, a plurality of columnar isolation structures and a plurality of conductive plugs. The bit lines are located on the substrate and extend along the first direction. The strip-shaped isolation structure is located at the ends of the bit lines and extends along the second direction, and the strip-shaped isolation structure includes a seam. In particular, the conductive residue is disposed in the seam. The columnar isolation structures are separated from each other and disposed between the bit lines. The conductive plugs are separated from each other and disposed between the bit lines, in which the conductive plugs and the conductive residue include the same conductive material.

    Memory Circuitry And Methods Used In Forming Memory Circuitry
    33.
    发明公开
    Memory Circuitry And Methods Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240224505A1

    公开(公告)日：2024-07-04

    申请号：US18527091

    申请日：2023-12-01

    申请人： Micron Technology, Inc.

    发明人： Jordan D. Greenlee ,  Ying Rui ,  Silvia Borsari ,  Prashant Raghu ,  Elisabeth Barr ,  Yen Ting Lin ,  Albert P. Chan ,  Martin Chen

    IPC分类号： H10B12/00

    CPC分类号： H10B12/33 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482

    摘要： A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Digitline structures are formed that are individually directly electrically coupled to the another source/drain regions of multiple of the transistors. The digitline structures individually comprise a conductive digitline and an insulator material thereatop. The insulator material has a top. First insulating material is formed directly above the tops of the insulator material and laterally-over longitudinal sides of the digitline structures and covers across the one source/drain regions laterally-between immediately-adjacent of the digitline structures. Second insulating material is formed over the first insulating material. The second insulating material has a maximum vertical thickness directly above the digitline structures that is greater than its minimum lateral thickness over the longitudinal sides of the digitline structures. The first insulating material is etched through to expose the one source/drain regions. Storage elements are formed that are individually electrically coupled to individual of the one source/drain regions. Other embodiments, including structure, are disclosed.

    Semiconductor Structure and Method of Making the Same
    35.
    发明公开
    Semiconductor Structure and Method of Making the Same 审中-公开

    公开(公告)号：US20240213152A1

    公开(公告)日：2024-06-27

    申请号：US17795117

    申请日：2022-06-10

    申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

    发明人： Tieh-Chiang Wu ,  Lingxin Zhu

    IPC分类号： H01L23/528 ,  H01L21/768 ,  H10B12/00

    CPC分类号： H01L23/528 ,  H01L21/76883 ,  H10B12/482

    摘要： A semiconductor structure and a preparation method making it are disclosed. The semiconductor structure includes: a substrate, a bit line contact structure, a first epitaxial layer, a bit line and a second epitaxial layer. The structure includes bit line contact holes. The bit line contact structure is disposed in one of the bit line contact holes. The first epitaxial layer is epitaxially grown on the sidewalls of the bit line contact structure. The bit line includes a connection layer connected to the bit line contact structure. The second epitaxial layer is epitaxially grown on the sidewalls of the connection layer. The present disclosure can reduce the contact resistance and parasitic capacitance between the bit line contact structures and the bit lines, thereby improving the electrical performance of the semiconductor structure, thereby raising the reliability and yield of the semiconductor structure.

    Semiconductor device and method for forming the same
    38.
    发明授权
    Semiconductor device and method for forming the same 有权

    公开(公告)号：US12016174B2

    公开(公告)日：2024-06-18

    申请号：US17673804

    申请日：2022-02-17

    申请人： Fujian Jinhua Integrated Circuit Co., Ltd.

    发明人： Min-Teng Chen

    IPC分类号： H10B12/00

    CPC分类号： H10B12/315 ,  H10B12/03 ,  H10B12/482

    摘要： A semiconductor device includes a substrate, a plurality of bit lines, a plurality of contacts, a plurality of storage node pads, a capacitor structure and a plurality of first interface layers. The bit lines and the contacts are disposed on the substrate, and the contacts are alternately and separately disposed with the bit lines. The storage node pads are disposed on the contacts and the bit lines, and are respectively aligned with the contacts. The capacitor structure is disposed on the storage node pads. The first interface layers are disposed between the storage node pads and the capacitor structure, and the first interface layers include a metal nitride material. The first interface layers may improve the granular size of the storage node pads, and reduce the surface roughness thereof, and further improve the electrical connection between the storage nodes and transistor components below.

    SEMICONDUCTOR DEVICE
    40.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240196599A1

    公开(公告)日：2024-06-13

    申请号：US18512135

    申请日：2023-11-17

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jaekang KOH ,  Byeongguk KO ,  Chanyoung KIM ,  Sangkoo NAM ,  Yongsoon CHOI

    IPC分类号： H10B12/00

    CPC分类号： H10B12/482 ,  H10B12/315

    摘要： A semiconductor device includes: an active pattern disposed on a substrate; a gate structure disposed on the active pattern; a bit line structure disposed on the active pattern, and including a first conductive pattern, a second conductive pattern and an insulation structure stacked on each other, a lower spacer structure disposed on a sidewall of the bit line structure; an upper spacer structure disposed on the lower spacer structure, wherein the upper spacer structure is disposed on an upper portion of the sidewall of the bit line structure; a contact plug structure disposed on the active pattern, wherein the contact plug structure is spaced apart from the bit line structure; and a capacitor disposed on the contact plug structure, wherein the lower spacer structure includes: a first spacer partially covering a sidewall of the first conductive pattern, and including air; and a second spacer disposed on the first spacer.