公开(公告)号：US5236852A

公开(公告)日：1993-08-17

申请号：US950333

申请日：1992-09-24

申请人： Michael Cherniawski ,  Jeffrey M. Barker ,  Ronald E. Pyle ,  Vidya S. Kaushik

发明人： Michael Cherniawski ,  Jeffrey M. Barker ,  Ronald E. Pyle ,  Vidya S. Kaushik

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/768 ,  H01L23/485

CPC分类号： H01L23/485 ,  H01L21/76838 ,  H01L2924/0002 ,  Y10S148/019

摘要： An electrical contact (46) to a phosphorous doped polysilicon gate electrode (18) is formed by preventing arsenic, from a source and drain implant, from doping a portion (22) of the polysilicon gate electrode (18). A photoresist mask (20) covers a portion (22) of the polysilicon gate electrode (18) during the implant, thus preventing it from being doped. An electrical contact (46) is then formed to the masked portion (22) of the polysilicon gate electrode (18).

公开(公告)号：US5227316A

公开(公告)日：1993-07-13

申请号：US744191

申请日：1991-08-12

申请人： Madhukar Vora ,  Greg Burton ,  Ashok Kapoor

发明人： Madhukar Vora ,  Greg Burton ,  Ashok Kapoor

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108 ,  H01L27/11

CPC分类号： H01L23/53271 ,  H01L21/28518 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S148/011 ,  Y10S148/019

摘要： There is disclosed herein a bipolar transistor structure having a self aligned extended silicide base contact. The contact extends to the position of a base contact window located outside the perimeter of the isolation island on a contact pad formed over the field oxide. This allows the size of the isolation island to be kept smaller and allows a smaller extrinsic base region to be formed. The base contact is formed of titanium and titanium silicide where the titanium/silicide boundary is self aligned with the edge of the device isolation island. The silicide is formed by reacting the titanium which completely covers the exposed epitaxial silicon inside the isolation island. An anisotropically etched oxide sidewall spacer insulates the silicide from the sidewall of the silicide-covered, polysilicon emitter contact.

公开(公告)号：US5208168A

公开(公告)日：1993-05-04

申请号：US617727

申请日：1990-11-26

申请人： Louis C. Parrillo ,  Neil B. Henis ,  Richard W. Mauntel

发明人： Louis C. Parrillo ,  Neil B. Henis ,  Richard W. Mauntel

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/74 ,  H01L21/768 ,  H01L23/522 ,  H01L27/08 ,  H01L29/36 ,  H01L29/78

CPC分类号： H01L29/36 ,  H01L21/743 ,  Y10S148/019 ,  Y10S148/02

摘要： Adjacent buried contacts (11, 12, 13) formed at the principal surface of a well or substrate region (14) of a semiconductor device, each having a doped contact region (29, 30 31) of one conductivity type and a punch-through prevention region (36, 37, 38) of the opposite conductivity type surrounding the lower portion of the doped contact region are provided. The punch-through prevention region may advantageously be of the same conductivity type as the substrate. By performing an extra implant or other impurity introduction step while the mask to etch the contacts through the dielectric layer remains in place, the procedure to provide punch-through protected buried contacts may be easily integrated into current processes without the need for an extra mask. Such a structure and procedure enables buried contacts to be spaced closely together without over-doping the well region (14) in which source-drain regions (40, 42, 44, 46) are also formed thus avoiding a degradation in device performance.

公开(公告)号：US5162263A

公开(公告)日：1992-11-10

申请号：US755820

申请日：1991-09-06

申请人： Iwao Kunishima ,  Tomonori Aoyama ,  Kyoichi Suguro

发明人： Iwao Kunishima ,  Tomonori Aoyama ,  Kyoichi Suguro

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L29/41 ,  H01L29/43 ,  H01L29/45 ,  H01L29/49

CPC分类号： H01L29/66272 ,  H01L21/2257 ,  H01L29/41 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66575 ,  Y10S148/019 ,  Y10S257/90

摘要： A semiconductor device comprises a semiconductor substrate of a first conductivity type. An insulative film and metal films are sequentially formed on the main top surface of the semiconductor substrate. Impurity diffusion layers of a second conductivity type are selectively formed on the main top surface of the semiconductor substrate. The semiconductor device further comprises metal compound layers consisting of constituting elements of the semiconductor substrate and a metal element. The metal compound layers are formed in the impurity diffusion layers in such a manner that they do not contact the insulative film, and the metal compound layers on the main back surface side of the semiconductor substrate have faces formed in parallel to the top surface of the semiconductor substrate. The method also includes cooling the top of the substrate to form a temperature gradient that results in increased dopant concentration at the bottom of a silicide layer.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底。 绝缘膜和金属膜依次形成在半导体衬底的主顶表面上。 第二导电类型的杂质扩散层选择性地形成在半导体衬底的主顶表面上。 半导体器件还包括由半导体衬底的构成元件和金属元素组成的金属化合物层。 金属化合物层以不与绝缘膜接触的方式形成在杂质扩散层中，并且半导体衬底的主背面侧上的金属化合物层具有平行于该半导体衬底的顶表面形成的面 半导体衬底。 该方法还包括冷却衬底的顶部以形成导致硅化物层底部的掺杂剂浓度增加的温度梯度。

公开(公告)号：US5075251A

公开(公告)日：1991-12-24

申请号：US404529

申请日：1989-09-08

申请人： Joaquim Torres ,  Jean Palleau ,  Noureddine Bourhila

发明人： Joaquim Torres ,  Jean Palleau ,  Noureddine Bourhila

IPC分类号： H01L21/28 ,  H01L21/285

CPC分类号： H01L21/28052 ,  H01L21/28518 ,  Y10S148/019 ,  Y10S148/147

摘要： A process for forming tungsten or molybdenum silicide on silicon apparent regions (6) of a silicon wafer surface (1) also comprising oxidized regions (2) includes the steps consisting in uniformly coating the wafer with a tungsten or molybdenum layer (10) and annealing at a temperature ranging from 700.degree. C. to 1000.degree. C. The annealing step is carried out in presence of a low pressure gas forming a chemical composite with tungsten or molybdenum. The composite is then selectively etched.

摘要翻译： 还包括氧化区域（2）的硅晶片表面（1）的硅表观区域（6）上形成钨或钼硅化物的方法包括以下步骤：用钨或钼层（10）均匀地涂覆晶片和退火 在700℃至1000℃的温度下进行。退火步骤在形成与钨或钼的化学复合物的低压气体存在下进行。 然后选择性地蚀刻复合材料。

公开(公告)号：US5001082A

公开(公告)日：1991-03-19

申请号：US337187

申请日：1989-04-12

申请人： Scott H. Goodwin-Johansson

发明人： Scott H. Goodwin-Johansson

IPC分类号： H01L21/285 ,  H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/665 ,  Y10S148/019 ,  Y10S148/116

摘要： A self-aligned salicide process produces small dimensioned semiconductor devices, for example metal oxide semiconductor (MOS) devices. An electrode is formed on the face of a semiconductor substrate, the electrode having a top and a sidewall and an insulating coating on the sidewall. Then a silicon layer and a refractory metal layer are formed on the face, top and sidewall, with one of the layers being continuous, and the other layer having a break on the sidewall. In a preferred embodiment the silicon layer is directionally applied, to form thick portions on the face and top and thin portion on the sidewall. The thin portion on the sidewall is removed and a metal layer is uniformly deposited. The substrate is heated to convert at least part of the silicon and metal layers to silicide. The silicide layer on the face is planar and does not consume the substrate at the face, allowing shallow source and drain regions to be formed.

摘要翻译： 自对准的自对准硅化物工艺生产小尺寸的半导体器件，例如金属氧化物半导体（MOS）器件。 电极形成在半导体衬底的表面上，电极具有顶部和侧壁以及侧壁上的绝缘涂层。 然后在表面，顶部和侧壁上形成硅层和难熔金属层，其中一层是连续的，另一层在侧壁上具有断裂。 在优选实施例中，硅层被定向地施加，以在侧壁上的表面和顶部以及薄的部分上形成厚的部分。 去除侧壁上的薄部分并均匀地沉积金属层。 将衬底加热以将至少部分硅和金属层转化为硅化物。 表面上的硅化物层是平面的，并且不消耗基板在表面，允许形成浅的源极和漏极区域。

公开(公告)号：US4992388A

公开(公告)日：1991-02-12

申请号：US444651

申请日：1989-12-10

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336

CPC分类号： H01L29/66606 ,  H01L21/28141 ,  H01L21/28525 ,  H01L29/66545 ,  Y10S148/019 ,  Y10S148/026

摘要： A process is disclosed for the fabrication of semiconductor devices which yields a device having a very short effective channel length and having polycrystalline source and drain electrodes. In accordance with the disclosed process, a semiconductor substrate is provided having a masking element positioned on the substrate surface. A layer of polycrystalline silicon is deposited on the exposed areas of the substrate surface by the process of selective deposition. The selectively deposited polycrystalline silicon is doped with conductivity determining impurities and that impurity material is thereafter redistributed to dope the underlying substrate to form source and drain regions. The masking element is removed to expose the portion of the semiconductor surface between the source and drain regions and to allow for a subsequent optional channel implantation. A gate insulator is formed overlying that portion between the source and drain regions and a second layer of silicon is deposited to overlay the gate insulator. The second layer of silicon is patterned to form the gate electrode of the insulated gate field effect transistor.

摘要翻译： 公开了一种用于制造半导体器件的工艺，该半导体器件产生具有非常短的有效沟道长度且具有多晶源极和漏极的器件。 根据所公开的方法，提供具有位于基板表面上的掩模元件的半导体基板。 通过选择性沉积的过程，在衬底表面的暴露区域上沉积多晶硅层。 选择性沉积的多晶硅掺杂有导电性确定杂质，然后将杂质材料重新分布以掺杂下面的衬底以形成源区和漏区。 去除掩模元件以暴露源极和漏极区域之间的半导体表面的部分并且允许随后的任选的沟道注入。 形成栅极绝缘体，覆盖源极和漏极区域之间的部分，并且沉积第二层硅以覆盖栅极绝缘体。 图案化第二层硅以形成绝缘栅场效应晶体管的栅电极。

公开(公告)号：US4897368A

公开(公告)日：1990-01-30

申请号：US195836

申请日：1988-05-19

申请人： Kazuhiro Kobushi ,  Shuichi Kameyama ,  Shozo Okada ,  Kazuhiko Tsuji

发明人： Kazuhiro Kobushi ,  Shuichi Kameyama ,  Shozo Okada ,  Kazuhiko Tsuji

IPC分类号： H01L21/28

CPC分类号： H01L21/28052 ,  Y10S148/019 ,  Y10S148/082 ,  Y10S148/114 ,  Y10S148/147 ,  Y10S438/914

摘要： Disclosed is a method of fabricating a polycidegate in semiconductor device which has a step of forming a conductor film of polysilicon on a substrate, a step of forming an ion implanted layer by implanting nitrogen ions into the polysilicon conductor film, and a step of forming a low resistance conductor film of titanium on the non-monocyrstalline conductor film. When a field effect transistor is formed by this method, using titanium nitride and/or TiSi.sub.2 alloy of the polysilicon conductor and low resistance conductor of titanium by heat treatment as a gate electrode material, the thickness of the alloyed layer is uniform, and breakdown of the gate insulating film due to local diffusion of low resistance conductor is not induced. In other embodiments, oxygen ions and silicon ions are also employed to form thin layers of tunnel oxide and amorphous silicon, respectively.

摘要翻译： 公开了一种在半导体器件中制造多晶硅封口的方法，该方法具有在衬底上形成多晶硅的导体膜的步骤，通过将氮离子注入多晶硅导体膜形成离子注入层的步骤，以及形成 非单晶硅导体膜上钛的低电阻导体膜。 当通过该方法形成场效应晶体管时，通过热处理将多晶硅导体和钛的低电阻导体的氮化钛和/或TiSi 2合金用作栅电极材料，合金层的厚度是均匀的，并且 不会引起由于低电阻导体的局部扩散而导致的栅极绝缘膜。 在其它实施例中，氧离子和硅离子也分别用于形成隧道氧化物和非晶硅的薄层。

公开(公告)号：US4882297A

公开(公告)日：1989-11-21

申请号：US205589

申请日：1988-06-13

申请人： Lothar Blossfeld

发明人： Lothar Blossfeld

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/331 ,  H01L21/768 ,  H01L29/73 ,  H01L29/732

CPC分类号： H01L21/76889 ,  H01L21/28518 ,  Y10S148/019 ,  Y10S148/105 ,  Y10S148/123 ,  Y10S148/124

摘要： In fabricating the contact, the electrode layer of polycrystalline silicon whose rim portion is bonded via a layer portion of insulating material to the substrate, is used at least throughout the length of a part of its rim portion for the lateral delimitation of a etching process, as an etch mask, in the course of which a frame-shaped layer portion is formed underneath the rim portion of the electrode layer, and the contact area of the substrate as bordering on the layer portion is exposed. Following the deposition of a metal layer of a metal forming a silicide in a thickness smaller than the thickness of the layer portion, and the heating for forming the silicide, the metal which has so far not reacted with the silicon, is removed by using an etching agent selectively dissolving the metal.

摘要翻译： 在制造接触时，其边缘部分经由绝缘材料的层部分结合到基底上的多晶硅的电极层至少在其边缘部分的整个长度上用于蚀刻工艺的横向限定， 作为蚀刻掩模，其中在电极层的边缘部分下方形成框状层部分，并暴露出与层部分相邻的基板的接触面积。 在形成厚度小于层部分厚度的硅化物的金属的金属层沉积之后，以及用于形成硅化物的加热，迄今未与硅反应的金属通过使用 蚀刻剂选择性地溶解金属。

公开(公告)号：US4877755A

公开(公告)日：1989-10-31

申请号：US200394

申请日：1988-05-31

申请人： Mark S. Rodder

发明人： Mark S. Rodder

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/49

CPC分类号： H01L29/6659 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/76895 ,  H01L29/4933 ,  Y10S148/019 ,  Y10S148/147

摘要： A MOS transistor (10) having a thicker silicide layer (50) over a gate (30) than a silicide layer (44) over source and drain regions (42) is disclosed. A process of the present invention forms a first silicide barrier (28) overlying the gate (30) when the gate is formed. Next, a first silicide formation process forms the first silicide layer (44) overlying source and drain regions (42). The silicide barrier layer (28) prevents silicide formation over the gate (30). The silicide barrier (28) is removed, and another silicide barrier (48) is formed over the first silicide layer (44). A second silicide formation process forms the second silicide layer (50) over the gate (30). The silicide barrier layer (48) prevents expansion of the first silicide layer (44).

摘要翻译： 公开了一种MOS晶体管（10），其在源极和漏极区域（42）上的硅化物层（44）上方的栅极（30）上具有较厚的硅化物层（50）。 当形成栅极时，本发明的方法形成了覆盖栅极（30）的第一硅化物屏障（28）。 接下来，第一硅化物形成工艺形成覆盖源区和漏区（42）的第一硅化物层（44）。 硅化物阻挡层（28）防止在栅极（30）上形成硅化物。 除去硅化物阻挡层（28），在第一硅化物层（44）上方形成另一硅化物屏障（48）。 第二硅化物形成工艺在栅极（30）上形成第二硅化物层（50）。 硅化物阻挡层（48）防止第一硅化物层（44）的膨胀。