公开(公告)号：US07660147B2

公开(公告)日：2010-02-09

申请号：US11959108

申请日：2007-12-18

Applicant: Te-Sheng Chao ,  Ming-Jung Chen ,  Philip H. Yeh ,  Ming-Jinn Tsai

Inventor： Te-Sheng Chao ,  Ming-Jung Chen ,  Philip H. Yeh ,  Ming-Jinn Tsai

IPC: G11C7/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: A programming method for a phase change memory based on the phase transformations between amorphous and crystalline phases is disclosed. The programming method comprises a current pulse with step waveform providing a first crystallization current pulse to the phase change memory and providing a second crystallization current pulse to the phase change memory. The first crystallization current pulse has a first rising edge, a first falling edge and a first peak current held for a first hold time. The second crystallization current pulse has a second peak current. The second peak current follows the first falling edge and is held for a second hold time.

Abstract translation: 公开了一种基于非晶相和晶相之间的相变的相变存储器的编程方法。 编程方法包括具有阶跃波形的电流脉冲，其向相变存储器提供第一结晶电流脉冲，并向相变存储器提供第二结晶电流脉冲。 第一结晶电流脉冲具有保持第一保持时间的第一上升沿，第一下降沿和第一峰值电流。 第二结晶电流脉冲具有第二峰值电流。 第二峰值电流遵循第一下降沿并保持第二保持时间。

公开(公告)号：US20090298284A1

公开(公告)日：2009-12-03

申请号：US12128434

申请日：2008-05-28

Applicant: TZU LUN CHENG ,  CHENG DA WU ,  DA YU CHUANG ,  WEI HENG LEE

Inventor： TZU LUN CHENG ,  CHENG DA WU ,  DA YU CHUANG ,  WEI HENG LEE

IPC: H01L21/44

CPC classification number: H01L21/28518

Abstract: A method for preparing an integrated circuit structure performs a deposition process to form a precursor layer on a substrate, and the precursor layer has a phase transition property in a transition temperature region. Subsequently, a first thermal treating process is performed at a first temperature to transform the precursor layer into a polymorphous layer possessing a predetermined crystalline phase, and the first temperature is higher than an upper limit of the temperature of the transition temperature region.

Abstract translation: 制备集成电路结构的方法执行沉积工艺以在衬底上形成前体层，并且前体层在转变温度区域中具有相变特性。 随后，在第一温度下进行第一热处理工艺，以将前体层转变为具有预定结晶相的多晶层，第一温度高于转变温度区域的温度的上限。

公开(公告)号：US20090296450A1

公开(公告)日：2009-12-03

申请号：US12344709

申请日：2008-12-29

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00 ,  G11C7/00 ,  G11C5/14

CPC classification number: G11C13/0069 ,  G11C5/147 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0064 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0066 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2029/5006

Abstract: A memory having a memory cell, a resistance estimator and a write current generator. The resistance estimator is coupled to the memory cell to estimate the resistance of the memory cell and outputs an estimated resistance level. According to the estimated resistance level, the write current generator generates a write current to flow through the memory cell and to change the resistance of the memory cell. The write current is in a pulse form, and the write current generator sets the pulse width, or magnitude, or both the pulse width and the magnitude of the write current according to the estimated resistance level.

Abstract translation: 具有存储单元的存储器，电阻估计器和写入电流发生器。 电阻估计器耦合到存储器单元以估计存储器单元的电阻并输出估计的电阻电平。 根据估计的电阻水平，写入电流发生器产生写入电流流过存储器单元并改变存储单元的电阻。 写入电流是脉冲形式，并且写入电流发生器根据估计的电阻电平设置脉冲宽度或幅度或脉冲宽度和写入电流的幅度。

公开(公告)号：US07569909B2

公开(公告)日：2009-08-04

申请号：US11745980

申请日：2007-05-08

Applicant: Chen-Ming Huang

Inventor： Chen-Ming Huang

IPC: H01L29/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/008 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device comprises a substrate. A dielectric layer is formed over the substrate and a phase change material layer is embedded in the dielectric layer. A first conductive electrode is also embedded in the dielectric layer to penetrate the phase change material layer and extends perpendicular to a top surface of the dielectric layer.

Abstract translation: 提供了相变存储器件及其制造方法。 相变存储器件的示例性实施例包括衬底。 介电层形成在衬底上，并且相变材料层嵌入电介质层中。 第一导电电极也嵌入电介质层中以穿透相变材料层并且垂直于电介质层的顶表面延伸。

公开(公告)号：US07569460B2

公开(公告)日：2009-08-04

申请号：US11583805

申请日：2006-10-20

Applicant: Sheng Da Tsai

Inventor： Sheng Da Tsai

IPC: H01L21/20

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10855 ,  H01L28/40

Abstract: A capacitor structure comprises a substrate having a contact plug, a conductive cylinder positioned on the substrate and an electroplating structure covering the conductive cylinder, wherein a bottom electrode of the capacitor structure comprises the conductive cylinder and the electroplating structure. The conductive cylinder can be a hollow conductive cylinder, and the electroplating structure comprises a first conductive layer covering the inner sidewall and bottom surface of the hollow conductive cylinder and a second conductive layer covering the first conductive layer and the outer sidewall of the hollow conductive cylinder. The conductive cylinder and the electroplating structure can be made of different conductive material, and the free end of the conductive cylinder is preferably round. The conductive cylinder can be made of titanium nitride or tantalum nitride, while the electroplating structure can be made of ruthenium or platinum.

Abstract translation: 电容器结构包括具有接触插塞的基板，位于基板上的导电圆柱体和覆盖导电圆柱体的电镀结构，其中电容器结构的底部电极包括导电圆柱体和电镀结构。 导电圆柱体可以是中空导电圆柱体，并且电镀结构包括覆盖中空导电圆柱体的内侧壁和底表面的第一导电层和覆盖中空导电圆柱体的第一导电层和外侧壁的第二导电层 。 导电圆柱体和电镀结构可以由不同的导电材料制成，并且导电圆筒的自由端优选为圆形。 导电圆柱体可由氮化钛或氮化钽制成，而电镀结构可由钌或铂制成。

公开(公告)号：US20090191686A1

公开(公告)日：2009-07-30

申请号：US12108330

申请日：2008-04-23

Applicant: Chun Yao Wang ,  Fu Hsiung Yang

Inventor： Chun Yao Wang ,  Fu Hsiung Yang

IPC: H01L21/02 ,  H01L21/3215

CPC classification number: H01L21/32155 ,  H01L27/1087 ,  H01L28/84 ,  H01L29/66181

Abstract: A method for preparing a doped polysilicon conductor according to this aspect of the present invention comprises the steps of (a) placing a substrate in a reaction chamber, (b) performing a deposition process to form a polysilicon layer on the substrate, (c) performing a grain growth process to form a plurality of polysilicon grains on the polysilicon layer, and (d) performing a dopant diffusion process to diffuse conductive dopants into the polysilicon layer via the polysilicon grains to form the doped polysilicon conductor.

Abstract translation: 根据本发明的这个方面的制备掺杂多晶硅导体的方法包括以下步骤：（a）将衬底放置在反应室中，（b）进行沉积工艺以在衬底上形成多晶硅层，（c） 进行晶粒生长处理以在所述多晶硅层上形成多个多晶硅晶粒，以及（d）进行掺杂剂扩散处理，以通过所述多晶硅晶粒将导电掺杂剂扩散到所述多晶硅层中，以形成所述掺杂多晶硅导体。

公开(公告)号：US20090189142A1

公开(公告)日：2009-07-30

申请号：US12324871

申请日：2008-11-27

Applicant: Frederick T. Chen

Inventor： Frederick T. Chen

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

Abstract: A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact.

Abstract translation: 公开了具有侧壁触点的相变存储元件，其具有底部电极。 在电极上形成非金属层，暴露电极顶表面的周边。 第一电接触在非金属层上以连接电极。 电介质层在第一电触头上并覆盖着。 第二电接触在介电层上。 开口通过第二电触点，电介质层和第一电触点，并且优选地通过非金属层与电极分离。 相变材料占据开口的一部分，其中第一和第二电触点在相变材料的侧壁处与相变材料接触。 可以在第二电接触件上形成第二非金属层。 顶部电极接触第二电触点的未完成端子的顶表面。

公开(公告)号：US20090189140A1

公开(公告)日：2009-07-30

申请号：US12020489

申请日：2008-01-25

Applicant: Frederick T. Chen

Inventor： Frederick T. Chen

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

Abstract: A phase-change memory element with side-wall contacts is disclosed. The phase-change memory element comprises a bottom electrode. A first dielectric layer is formed on the bottom electrode. A first electrical contact is formed on the first dielectric layer and electrically connects to the bottom electrode. A second dielectric layer is formed on the first electrical contact. A second electrical contact is formed on the second dielectric layer, wherein the second electrical contact comprises an outstanding terminal. An opening passes through the second electrical contact, the second dielectric layer, and the first electrical contact. A phase-change material occupies at least one portion of the opening. A third dielectric layer is formed on and covers the second electrical contact, exposing a top surface of outstanding terminal. A top electrode is formed on the third dielectric layer, contacting the outstanding terminal.

Abstract translation: 公开了一种具有侧壁触点的相变存储元件。 相变存储元件包括底电极。 第一电介质层形成在底电极上。 第一电接触形成在第一电介质层上并电连接到底电极。 在第一电触点上形成第二电介质层。 第二电接触形成在第二电介质层上，其中第二电接触包括未完成的端子。 开口穿过第二电触点，第二电介质层和第一电触头。 相变材料占据开口的至少一部分。 第三电介质层形成在并覆盖第二电触点，露出未完成端子的顶表面。 顶部电极形成在第三电介质层上，与未完成的端子接触。

公开(公告)号：US07566895B2

公开(公告)日：2009-07-28

申请号：US11753528

申请日：2007-05-24

Applicant: Wei-Su Chen

Inventor： Wei-Su Chen

IPC: H01L29/02

CPC classification number: G11C13/0004 ,  H01L27/2409 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1691

Abstract: A phase change memory device is provided. The phase change memory device includes a substrate comprising a stacked structure. The stacked structure comprises a plurality of insulating layers and conductive layers. Any two of the conductive layers are spaced apart by one of the conductive layers. A first electrode structure with a first sidewall and a second sidewall is formed on the stacked structure. A plurality of heating electrodes is placed on the conductive layers and adjacent to the first sidewall and the second sidewall of the first electrode structure. A pair of phase change material spacers is placed on the first sidewall and the second sidewall of the first electrode structure. The phase change material sidewalls cover the plurality of heating electrodes.

Abstract translation: 提供了一种相变存储器件。 相变存储器件包括包括堆叠结构的衬底。 堆叠结构包括多个绝缘层和导电层。 导电层中的任何两个由一个导电层隔开。 具有第一侧壁和第二侧壁的第一电极结构形成在堆叠结构上。 多个加热电极放置在导电层上并与第一电极结构的第一侧壁和第二侧壁相邻。 一对相变材料间隔物被放置在第一电极结构的第一侧壁和第二侧壁上。 相变材料侧壁覆盖多个加热电极。

公开(公告)号：US20090130818A1

公开(公告)日：2009-05-21

申请号：US12022044

申请日：2008-01-29

Applicant: TSUNG TE LIN

Inventor： TSUNG TE LIN

IPC: H01L21/283 ,  H01L21/762

CPC classification number: H01L21/76224

Abstract: A method for preparing a recessed gate structure comprises the steps of: forming a shallow trench isolation structure surrounding an active area in a silicon substrate, wherein an etching barrier layer is formed on the surface of the shallow trench isolation structure; forming a plurality of gate trenches in the active area of the silicon substrate by performing an etching process; and forming a recessed gate structure by filling the gate trench with a predetermined height.

Abstract translation: 一种用于制备凹陷栅极结构的方法包括以下步骤：形成围绕硅衬底中的有源区的浅沟槽隔离结构，其中在浅沟槽隔离结构的表面上形成蚀刻阻挡层; 通过进行蚀刻工艺在硅衬底的有源区中形成多个栅极沟槽; 以及通过以预定高度填充所述栅极沟槽来形成凹陷栅极结构。