公开(公告)号：US20070019681A1

公开(公告)日：2007-01-25

申请号：US11511623

申请日：2006-08-29

Applicant: Xianbin Wang

Inventor： Xianbin Wang

IPC: H04J1/02

CPC classification number: H04L5/143 ,  H04L5/023

Abstract: To improve the performance of DSL modems, a DSL duplexing ratio for a new communication is selected according to the communications needs of an application. A required upstream and downstream bit rate for application communications is determined. From the ratio of these bit rates, a desired duplexing ratio is calculated. The operation of the modem is then adapted to choose a duplexing ratio that approximates the desired duplexing ratio for the application. To optimize modem operation, the size and position of the upstream and downstream bandwidths used for transmission are intelligently selected when the bit rate necessary for making the transmission is less than the total available bandwidth provided by the chosen duplexing ratio. By intelligently selecting a minimum number of subcarriers for Digital Multi-tone (DMT) signal transmission, a reduction in line driver power consumption is effectuated. Additionally, by intelligently selecting the position of the used bandwidth within the total available bandwidth, near-end crosstalk (NEXT) noise may be minimized.

Abstract translation: 为了提高DSL调制解调器的性能，根据应用的通信需要选择新通信的DSL双工比。 确定应用通信所需的上行和下行比特率。 根据这些比特率的比率，计算期望的双工比。 调制解调器的操作然后适于选择近似于应用的期望双工比的双工比率。 为了优化调制解调器操作，当用于进行传输所需的比特率小于由选择的双工比提供的总可用带宽时，用于传输的上行和下行带宽的大小和位置被智能地选择。 通过智能地选择用于数字多音（DMT）信号传输的最小数量的子载波，实现了线路驱动器功耗的降低。 此外，通过智能地选择所使用的带宽在总可用带宽内的位置，近端串扰（NEXT）噪声可能被最小化。

公开(公告)号：US20070001286A1

公开(公告)日：2007-01-04

申请号：US11517879

申请日：2006-09-08

Applicant: Anthony Chiu ,  Tom Lao

Inventor： Anthony Chiu ,  Tom Lao

IPC: H01L23/12

CPC classification number: H01L23/562 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/854 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/341 ,  H05K2203/1178 ,  H05K2203/304 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A system and method is disclosed for venting pressure from an integrated circuit package that is sealed with a lid. During a surface mount process for mounting a ball grid array integrated circuit package to a circuit board the application of heat (1) weakens the solder that seals a soldered lid, and (2) increases vapor pressure within the integrated circuit package. This may cause the soldered lid to move out of its soldered position. The present invention solves this problem by providing an integrated circuit with a solder mask that has a plurality of solder mask vents that form a plurality of vapor pressure vents through the solder. The vapor pressure vents prevent the occurrence of any increase in vapor pressure that would shift the soldered lid out of its soldered position. An alternate embodiment vents pressure through an epoxy layer that is used to attach a lid by epoxy.

Abstract translation: 公开了一种用于从由盖子密封的集成电路封装件排出压力的系统和方法。 在用于将球栅阵列集成电路封装安装到电路板的表面安装过程中，加热（1）的作用削弱了密封焊接盖的焊料，和（2）增加集成电路封装内的蒸汽压力。 这可能导致焊接的盖子从其焊接位置移出。 本发明通过提供具有焊料掩模的集成电路来解决这个问题，该焊接掩模具有多个通过焊料形成多个蒸汽压力通气口的焊接掩模排出口。 蒸汽压力通风口防止蒸汽压力的任何增加的发生，这将使焊接的盖子从其焊接位置移位。 替代实施例通过用于通过环氧树脂附接盖子的环氧树脂层排出压力。

公开(公告)号：US07159073B2

公开(公告)日：2007-01-02

申请号：US10401507

申请日：2003-03-27

Applicant: Alan Longo ,  Glen Catalano ,  Brett Lammers ,  Glenn Alan Lott ,  William Morgan Tempero ,  Aaron Wade Wilson

Inventor： Alan Longo ,  Glen Catalano ,  Brett Lammers ,  Glenn Alan Lott ,  William Morgan Tempero ,  Aaron Wade Wilson

IPC: G06F12/00

CPC classification number: G06F12/0871 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0676 ,  G06F2212/312 ,  G06F2212/462

Abstract: An extent record for an extent based data buffer that includes a host pointer that links the extent record to a next host extent record of a host extent record set, and a storage device pointer that links the extent record to a next storage device extent record of a storage device extent record set. Also, a system for transferring data between a host and a storage device that includes a data buffer coupled to the host and the storage device, where memory in the data buffer is divided into one or more extents, an extent table associated with the data buffer, where the extent table includes at least one extent record, an LBA chain table coupled to the host and the extent table, and a track section table coupled to the storage device and the extent table.

Abstract translation: 用于基于盘区的数据缓冲器的盘区记录，其包括将盘区记录链接到主盘区记录集的下一个主机盘区记录的主机指针，以及将盘区记录链接到下一个存储设备盘区记录的存储设备指针 存储设备盘区记录集。 而且，一种用于在主机和存储设备之间传送数据的系统，该系统包括耦合到主机和存储设备的数据缓冲器，其中数据缓冲器中的存储器被分成一个或多个盘区，与数据缓冲器相关联的盘区表 其中所述盘区表包括至少一个盘区记录，耦合到所述主机的LBA链表和所述盘区表，以及耦合到所述存储设备和所述盘区表的跟踪段表。

公开(公告)号：US20060292842A1

公开(公告)日：2006-12-28

申请号：US11469361

申请日：2006-08-31

Applicant: Robert Hodges

Inventor： Robert Hodges

IPC: H01L29/76 ,  H01L21/3205

CPC classification number: H01L29/66583 ,  H01L21/26586 ,  H01L29/66537 ,  H01L29/66553

Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then forms openings in a top one of the layers. A blanket dielectric layer is formed in the openings and on the layers. Anisotropic etching removes portions of the blanket dielectric layer from planar surfaces of the substrate but not from sidewalls of the openings to form dielectric spacers separated by gaps within the openings. Gate oxides are formed by oxidation of exposed areas of the substrate. Ion implantation forms channels beneath the gate oxides. Polysilicon deposition followed by chemical-mechanical polishing defines gates in the gaps. The chemically distinct layers are then stripped without removing the dielectric spacers. Conventional fabrication operations define other structures to complete fabrication of an integrated circuit.

Abstract translation: 半导体结构包括第一导电类型的硅衬底，其包括形成在其表面上的第二导电类型的阱。 井可以通过浅沟槽隔离来横向隔离。 通过首先形成几个化学上不同的层，在孔中形成晶体管。 然后各向异性蚀刻在顶层中形成开口。 在开口和层上形成覆盖层的介电层。 各向异性蚀刻从衬底的平面表面除去橡皮布介电层的部分，但不从开口的侧壁移除，以形成由开口内的间隙分隔的电介质隔离层。 栅极氧化物通过氧化底物的暴露区域而形成。 离子注入在栅极氧化物下形成通道。 多晶硅沉积随后化学机械抛光定义了间隙中的浇口。 然后剥离化学上不同的层，而不去除电介质间隔物。 传统的制造操作定义了完成集成电路制造的其它结构。

公开(公告)号：US07143268B2

公开(公告)日：2006-11-28

申请号：US09751674

申请日：2000-12-29

Applicant: Paolo Faraboschi ,  Anthony X. Jarvis ,  Mark Owen Homewood ,  Geoffrey M. Brown ,  Gary L. Vondran

Inventor： Paolo Faraboschi ,  Anthony X. Jarvis ,  Mark Owen Homewood ,  Geoffrey M. Brown ,  Gary L. Vondran

IPC: G06F9/30

CPC classification number: G06F9/3891 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/3853 ,  G06F9/3885

Abstract: A data processor includes execution clusters, an instruction cache, an instruction issue unit, and alignment and dispersal circuitry. Each execution cluster includes an instruction execution pipeline having a number of processing stages, and each execution pipeline is a number of lanes wide. The processing stages execute instruction bundles, where each instruction bundle has one or more syllables. Each lane is capable of receiving one of the syllables of an instruction bundle. The instruction cache includes a number of cache lines. The instruction issue unit receives fetched cache lines and issues complete instruction bundles toward the execution clusters. The alignment and dispersal circuitry receives the complete instruction bundles from the instruction issue unit and routes each received complete instruction bundle to a correct one of the execution clusters. The complete instruction bundles are routed as a function of at least one address bit associated with each complete instruction bundle.

Abstract translation: 数据处理器包括执行集群，指令高速缓存，指令发布单元以及对准和分散电路。 每个执行集群包括具有多个处理阶段的指令执行流水线，并且每个执行流水线都是多个通道。 处理阶段执行指令束，其中每个指令束具有一个或多个音节。 每个通道能够接收指令束的一个音节。 指令高速缓存包含多条缓存行。 指令发布单元接收获取的高速缓存行并向执行群发出完整的指令束。 对齐和分散电路从指令发布单元接收完整的指令束，并将每个接收的完整指令包路由到正确的一个执行簇。 完整的指令束作为与每个完整指令束相关联的至少一个地址位的功能进行路由。

公开(公告)号：US20060255455A1

公开(公告)日：2006-11-16

申请号：US11263115

申请日：2005-10-31

Applicant: Craig Rotay

Inventor： Craig Rotay

IPC: H01L23/34

CPC classification number: H01L23/49562 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/3426 ,  H05K2201/10166 ,  H05K2201/10818 ,  H05K2201/1084 ,  Y02P70/613 ,  H01L2924/00

Abstract: A high power density transistor structure includes a transistor package capable of housing a high power density transistor. The transistor package has a package insulator and a plurality of transistor leads. Each of the transistor leads has a far end, a near end and a lead periphery. The high power density transistor structure also includes a solder lock located on at least one of the transistor leads. At least a portion of the solder lock is attachable to a printed circuit board (PCB). At least a portion of the lead periphery of each transistor lead is attachable to at least one of: the PCB and the package insulator.

Abstract translation: 高功率密度晶​​体管结构包括能够容纳高功率密度晶​​体管的晶体管封装。 晶体管封装具有封装绝缘体和多个晶体管引线。 每个晶体管引线具有远端，近端和引线周边。 高功率密度晶​​体管结构还包括位于至少一个晶体管引线上的焊接锁。 焊接锁的至少一部分可附接到印刷电路板（PCB）。 每个晶体管引线的引线周边的至少一部分可附接到PCB和封装绝缘体中的至少一个。

公开(公告)号：US20060246865A1

公开(公告)日：2006-11-02

申请号：US11480205

申请日：2006-06-29

Applicant: Aleksej Makarov

Inventor： Aleksej Makarov

IPC: H04B1/10

CPC classification number: H04L27/2332 ,  H04L27/2275 ,  H04L2027/0065 ,  H04L2027/0087

Abstract: Counter-clockwise and clockwise quadrant transitions are detected and accumulated with respect to a received complex signal over a certain time period. These transitions may then be compared in order to obtain information indicative of both a magnitude and phase of a frequency offset error. Additionally, zero-crossings of the received complex signal over the same certain time period are detected and accumulated. The accumulated crossings provide information indicative of frequency offset magnitude. The determined magnitude and phase of the frequency offset error may then be used to adjust a local oscillator frequency to provide for improved receiver performance.

公开(公告)号：US07126984B2

公开(公告)日：2006-10-24

申请号：US10029190

申请日：2001-12-19

Applicant: Xianbin Wang

Inventor： Xianbin Wang

IPC: H04B1/38

CPC classification number: H04L5/0064 ,  H04L5/0007 ,  H04L5/0046 ,  H04L5/006 ,  H04L5/0062 ,  H04M3/007 ,  H04M3/18 ,  H04M11/062

Abstract: To optimize the performance of DSL modems in the same cable bundle, the size and position of the bandwidth used for transmission is intelligently selected when the bit rate necessary for making the transmission is less than the total available bandwidth. By intelligently selecting a minimum number of subcarriers for Digital Multi-tone (DMT) signal transmission, a reduction in line driver power consumption is effectuated. Additionally, by intelligently selecting the position of the used bandwidth within the total available bandwidth, near-end crosstalk (NEXT) noise within the cable bundle may be minimized.

公开(公告)号：US20060227070A1

公开(公告)日：2006-10-12

申请号：US11100044

申请日：2005-04-06

Applicant: Eric Danstrom

Inventor： Eric Danstrom

IPC: G09G3/14

CPC classification number: G09G3/32 ,  G09G2320/0626

Abstract: A plurality of grids of LED segments form an LED array. Each grid includes a plurality of LED segments connected in a common cathode configuration at a common cathode node. A high side driver is connected to all of the plurality of grids. This high side driver is operable responsive to segment control signals to selectively supply current to certain LED segments. One low side driver is provided for each of the plurality of grids. Each low side driver is responsive to a grid control signal to make a grid selection and sink current from the common cathode node of its corresponding selected grid of LED segments. A plurality of selectively actuated current sink paths are provided in each low side driver. A control logic circuit actuates a current sink path within the low side driver for each LED segment that is selectively supplied current by the high side driver. A substantially constant low side voltage drop through these sink paths is provided regardless of the number of LED segments that are supplied current by the high side driver so as to achieve a substantially constant LED segment brightness. A common anode configuration operating in an analogous way is also disclosed.

Abstract translation: 多个LED段的栅格形成LED阵列。 每个栅格包括在公共阴极节点处以公共阴极配置连接的多个LED段。 高侧驱动器连接到所有多个网格。 该高侧驱动器响应于段控制信号而可操作地选择性地向某些LED段提供电流。 为多个网格中的每一个提供一个低侧驱动器。 每个低侧驱动器响应于电网控制信号以从其相应的所选LED段格栅的公共阴极节点进行网格选择和吸收电流。 在每个低侧驱动器中设置有多个选择性致动的电流槽路径。 控制逻辑电路为每个LED段致动低侧驱动器内的电流吸收通路，每个LED段由高侧驱动器选择性供电。 无论高侧驱动器为电流提供的LED段的数量如何，都提供通过这些汇流通路的基本恒定的低侧电压降，以实现基本恒定的LED段亮度。 还公开了以类似方式操作的常见阳极配置。

公开(公告)号：US07109574B2

公开(公告)日：2006-09-19

申请号：US10400207

申请日：2003-03-27

Applicant: Anthony M. Chiu ,  Harry Michael Siegel

Inventor： Anthony M. Chiu ,  Harry Michael Siegel

IPC: H01L23/06 ,  H01L23/50 ,  H01L29/40

CPC classification number: H01L24/48 ,  G06K9/0002 ,  H01L21/565 ,  H01L23/3107 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4848 ,  H01L2224/85051 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: An integrated circuit (IC) device comprising: 1) an integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and sidewalls extending between the first surface and the second surface; 2) an integrated circuit (IC) package for supporting the IC die, wherein the IC package is attached to at least one of the sidewalls of the IC die such that at least a portion of the IC die first surface and at least a portion of the IC die second surface are exposed; and 3) at least one auxiliary component attached to at least one of the exposed portion of the IC die first surface and the exposed portion of the IC die second surface.

Abstract translation: 1.一种集成电路（IC）装置，包括：1）具有第一表面，与第一表面相对的第二表面和在第一表面和第二表面之间延伸的侧壁的集成电路（IC）模具; 2）一种用于支持IC芯片的集成电路（IC）封装，其中IC封装被附接到IC芯片的至少一个侧壁，使得IC的至少一部分裸片的第一表面和至少一部分 IC芯片第二表面露出; 以及3）至少一个辅助部件，其附接到IC管芯第一表面的暴露部分和IC裸片第二表面的暴露部分中的至少一个。