公开(公告)号：US20220147668A1

公开(公告)日：2022-05-12

申请号：US17094690

申请日：2020-11-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Nicholas Malaya ,  Jakub Kurzak

IPC: G06F30/27 ,  G06F17/18 ,  G06K9/62

Abstract: Techniques are disclosed for compressing data. The techniques include identifying, in data to be compressed, a first set of values, wherein the first set of values include a first number of two or more consecutive identical non-zero values; including, in compressed data, a first control value indicating the first number of non-zero values and a first data item corresponding to the consecutive identical non-zero values; identifying, in the data to be compressed, a second value having an exponent value included in a defined set of exponent values; including, in the compressed data, a second control value indicating the exponent value and a second data item corresponding to a portion of the second value other than the exponent value; and including, in the compressed data, a third control value indicating a third set of one or more consecutive zero values in the data to be compressed.

公开(公告)号：US11321241B2

公开(公告)日：2022-05-03

申请号：US17008435

申请日：2020-08-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  Michael W. LeBeane

IPC: G06F12/1027 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/126 ,  G06F12/0846

Abstract: Techniques are disclosed for processing address translations. The techniques include detecting a first miss for a first address translation request for a first address translation in a first translation lookaside buffer, in response to the first miss, fetching the first address translation into the first translation lookaside buffer and evicting a second address translation from the translation lookaside buffer into an instruction cache or local data share memory, detecting a second miss for a second address translation request referencing the second address translation, in the first translation lookaside buffer, and in response to the second miss, fetching the second address translation from the instruction cache or the local data share memory.

公开(公告)号：US20220130342A1

公开(公告)日：2022-04-28

申请号：US17134770

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： ASHISH JAIN ,  DHIRENDRA PARTAP SINGH RANA ,  SAMUEL NAFFZIGER ,  GIA TUNG PHAN ,  BENJAMIN TSIEN

IPC: G09G3/36 ,  G09G3/20 ,  G06F12/0895 ,  G06F12/0811 ,  G06F1/3234

Abstract: Refreshing displays using on-die cache, including: determining that a static display condition has been met; storing, in cache memory of a processor, first display data; and displaying the first display data from the cache memory.

公开(公告)号：US20220129752A1

公开(公告)日：2022-04-28

申请号：US17571045

申请日：2022-01-07

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Sateesh Lagudu ,  Lei Zhang ,  Allen Rush

IPC: G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06F1/3296

Abstract: Systems, apparatuses, and methods for implementing memory bandwidth reduction techniques for low power convolutional neural network inference applications are disclosed. A system includes at least a processing unit and an external memory coupled to the processing unit. The system detects a request to perform a convolution operation on input data from a plurality of channels. Responsive to detecting the request, the system partitions the input data from the plurality of channels into 3D blocks so as to minimize the external memory bandwidth utilization for the convolution operation being performed. Next, the system loads a selected 3D block from external memory into internal memory and then generates convolution output data for the selected 3D block for one or more features. Then, for each feature, the system adds convolution output data together across channels prior to writing the convolution output data to the external memory.

公开(公告)号：US11315883B2

公开(公告)日：2022-04-26

申请号：US16680978

申请日：2019-11-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Suming Hu ,  Roden Topacio ,  Farshad Ghahghahi ,  Jianguo Li ,  Andrew Kwan Wai Leung

IPC: H01L23/544 ,  H01L23/18 ,  H01L23/12

Abstract: An apparatus includes a substrate including an identification code on a first side of the substrate and near a perimeter of the substrate. The apparatus includes a stiffener structure attached to the first side of the substrate. The stiffener structure has a cutout in an outer perimeter of the stiffener structure. The stiffener structure is oriented with respect to the substrate to cause the cutout to expose the identification code. The cutout may have a first dimension and a second dimension orthogonal to the first dimension. The first dimension may exceed a corresponding first dimension of the identification code and the second dimension may exceed a corresponding second dimension of the identification code, thereby forming a void region between the identification code and edges of the stiffener structure.

公开(公告)号：US20220122652A1

公开(公告)日：2022-04-21

申请号：US17564575

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Kedarnath Balakrishnan ,  Jing Wang ,  Guanhao Shen

IPC: G11C11/406

Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

公开(公告)号：US11301410B1

公开(公告)日：2022-04-12

申请号：US17120208

申请日：2020-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Gordon Caruk

IPC: G06F13/42 ,  G06F9/54 ,  G06F13/40 ,  G06F15/173 ,  G06F13/364

Abstract: An electronic device includes a requester and a link interface coupled between the requester and a link. The requester is configured to send a request packet to a completer on the link via the link interface. When sending the request packet to the completer, the requester sends, to the completer via the link interface, the request packet with a tag that is not unique with respect to tags in other request packets from the requester that will be in the internal elements of the completer before the request packet is in the internal elements of the completer, but that is unique with respect to tags in other request packets from the requester that will be in the internal elements of the completer while the request packet is in the internal elements of the completer.

公开(公告)号：US11295507B2

公开(公告)日：2022-04-05

申请号：US17091957

申请日：2020-11-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark Leather ,  Michael Mantor

IPC: G06T15/00 ,  G06F9/48 ,  G06T1/20

Abstract: A graphics processing unit (GPU) or other apparatus includes a plurality of shader engines. The apparatus also includes a first front end (FE) circuit and one or more second FE circuits. The first FE circuit is configured to schedule geometry workloads for the plurality of shader engines in a first mode. The first FE circuit is configured to schedule geometry workloads for a first subset of the plurality of shader engines and the one or more second FE circuits are configured to schedule geometry workloads for a second subset of the plurality of shader engines in a second mode. In some cases, a partition switch is configured to selectively connect the first FE circuit or the one or more second FE circuits to the second subset of the plurality of shader engines depending on whether the apparatus is in the first mode or the second mode.

公开(公告)号：US20220103191A1

公开(公告)日：2022-03-31

申请号：US17125145

申请日：2020-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Shrikanth Ganapathy ,  John Kalamatianos

IPC: H03M13/35 ,  G06F11/10 ,  G06F12/0895

Abstract: Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.

公开(公告)号：US20220100813A1

公开(公告)日：2022-03-31

申请号：US17032314

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sateesh LAGUDU ,  Allen H. RUSH ,  Michael MANTOR ,  Arun Vaidyanathan ANANTHANARAYAN ,  Prasad NAGABHUSHANAMGARI

IPC: G06F17/16 ,  G06F13/28

Abstract: An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that are dynamically mapped to mutually exclusive subsets of the rows and columns of the processor element arrays based on dimensions of matrices that provide the parameter values to the processor element arrays. In some cases, the processor element arrays are vector arithmetic logic unit (ALU) processors and the memory interfaces are direct memory access (DMA) engines. The rows of the processor element arrays in the subsets are mutually exclusive to the rows in the other subsets and the columns of the processor element arrays in the subsets are mutually exclusive to the columns in the other subsets. The matrices can be symmetric or asymmetric, e.g., one of the matrices can be a vector having a single column.