公开(公告)号：US07915908B2

公开(公告)日：2011-03-29

申请号：US12037319

申请日：2008-02-26

Applicant: Alberto Pagani

Inventor： Alberto Pagani

IPC: G01R31/02 ,  G01R31/26

CPC classification number: G01R31/2851 ,  G01R31/2886 ,  G01R31/3025 ,  G01R31/303 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.

Abstract translation: 一种集成在半导体材料裸片上并适于至少部分地被无线测试的集成电路，其中用于设置用于集成电路的无线测试的所选无线电通信频率的电路集成在半导体材料裸片上。

公开(公告)号：US20110062601A1

公开(公告)日：2011-03-17

申请号：US12949314

申请日：2010-11-18

Applicant: Fabrice Marinet

Inventor： Fabrice Marinet

IPC: H01L23/50

CPC classification number: H01L23/544 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of at least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier.

Abstract translation: 产生支持至少一个集成电路的芯片标识符，其包括通过切割芯片提供至少一个导电路径的切口，切割线相对于芯片的位置调节该标识符。

公开(公告)号：US07902621B2

公开(公告)日：2011-03-08

申请号：US12398872

申请日：2009-03-05

Applicant: Perceval Coudrain ,  Philippe Coronel ,  Michel Marty ,  Matthieu Bopp

Inventor： Perceval Coudrain ,  Philippe Coronel ,  Michel Marty ,  Matthieu Bopp

IPC: H01L31/0232 ,  H01L27/14 ,  H01L31/00 ,  H01L31/06 ,  H01L27/15

CPC classification number: H01L27/14625 ,  H01L27/14645 ,  H01L27/14683 ,  H01L31/0232

Abstract: A semiconductor structure including a first active area under which is buried a first reflective layer and a least one second active area under which is buried a second reflective layer, wherein the upper surface of the second reflective layer is closer to the upper surface of the structure than the upper surface of the first reflective layer.

Abstract translation: 一种半导体结构，包括第一有源区，其下埋有第一反射层和至少一个第二有源区，在该第一有源区内掩埋有第二反射层，其中第二反射层的上表面更靠近该结构的上表面 比第一反射层的上表面。

公开(公告)号：US07885408B2

公开(公告)日：2011-02-08

申请号：US10903525

申请日：2004-07-30

Applicant: Yannick Teglia ,  Pierre-Yvan Liardet

Inventor： Yannick Teglia ,  Pierre-Yvan Liardet

IPC: H04K1/02 ,  H04K3/00 ,  G06F12/14

CPC classification number: H04L9/003 ,  H04L9/302 ,  H04L2209/046 ,  H04L2209/08

Abstract: A method for masking several identical functional processes manipulating digital data, including dividing the functional processes into steps at the end of each of which the process can be interrupted with the storage of at least one intermediary result, and successively executing the steps of at least two processes and selecting, at each step end, the process of the next step according to the result of a non-deterministic drawing of a number.

Abstract translation: 一种用于屏蔽操纵数字数据的几个相同的功能过程的方法，包括将功能过程划分成每个结尾处的步骤，其中过程可以通过存储至少一个中间结果而被中断，并且连续执行至少两个步骤 根据数字的非确定性绘制的结果在每个步骤结束处理和选择下一步骤的处理。

公开(公告)号：US07883906B2

公开(公告)日：2011-02-08

申请号：US12716289

申请日：2010-03-03

Applicant: Ludovic Goux ,  Monique Gervais

Inventor： Ludovic Goux ,  Monique Gervais

IPC: H01L29/72

CPC classification number: H01L28/55 ,  H01L28/60

Abstract: The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate.

Abstract translation: 使用导电二维钙钛矿作为硅，金属或非晶氧化物衬底之间的界面和通过外延沉积的绝缘钙钛矿，以及集成电路及其制造方法，其包括通过外延沉积的绝缘钙钛矿层以形成 电容元件的电介质至少具有由导电二维钙钛矿形成的电极，其形成在所述电介质和下面的硅，金属或非晶氧化物衬底之间的界面。

公开(公告)号：US07880268B2

公开(公告)日：2011-02-01

申请号：US11746177

申请日：2007-05-09

Applicant: Sébastien Cremer ,  Cédric Perrot ,  Claire Richard

Inventor： Sébastien Cremer ,  Cédric Perrot ,  Claire Richard

IPC: H01L49/02 ,  H01L21/64

CPC classification number: H01L28/91 ,  H01L27/10829

Abstract: A method for forming a MIM-type capacitor by filling of trenches by conformal depositions of insulating materials and of conductive materials, two successive electrodes of the capacitor including on either side of a thin vertical insulating layer at least one conductive layer of same nature, including the step of lowering the level of the conductive layers with respect to the level of the insulating layer separating them.

Abstract translation: 一种用于通过绝缘材料和导电材料的共形沉积填充沟槽来形成MIM型电容器的方法，所述电容器的两个连续电极包括在薄垂直绝缘层的至少一个相同性质的导电层的任一侧上，包括 相对于分离它们的绝缘层的水平降低导电层的水平的步骤。

公开(公告)号：US07873191B2

公开(公告)日：2011-01-18

申请号：US11420152

申请日：2006-05-24

Applicant: Jérôme Bach

Inventor： Jérôme Bach

IPC: G06K9/00 ,  H01G5/01 ,  G01P15/125 ,  G01R27/28

CPC classification number: H01L23/5223 ,  H01G4/38 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitive array comprising at least two capacitive entities, comprising a substrate layer. The substrate layer comprises a comb comprising at least four substantially identical teeth, and, for each capacitive entity, a set of fingers comprising one or more interlinked fingers. At least two sets of fingers comprise a different number of fingers, each finger being nested between two teeth of the comb and being substantially identical to the other fingers. The fingers of each set of fingers are substantially distributed symmetrically relative to a median axis of the comb. The comb and the fingers are integrated in a single block.

Abstract translation: 一种包括至少两个电容性实体的电容阵列，包括基底层。 衬底层包括包括至少四个基本上相同的齿的梳子，并且对于每个电容实体，包括一个或多个互连的手指的一组手指。 至少两组手指包括不同数量的手指，每个手指嵌套在梳子的两个齿之间并且基本上与其他手指相同。 每组手指的手指相对于梳子的中轴线对称地基本分布。 梳子和手指集成在一个单独的块中。

公开(公告)号：US07872894B2

公开(公告)日：2011-01-18

申请号：US12421821

申请日：2009-04-10

Applicant: Philippe Roche ,  Francois Jacquet

Inventor： Philippe Roche ,  Francois Jacquet

IPC: G11C5/06

CPC classification number: G11C11/4125 ,  G11C5/005

Abstract: A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.

Abstract translation: 存储器单元被保护以防止电流或电压尖峰。 小区包括用于在至少一对互补节点中存储信息的一组冗余数据存储节点。 小区还包括用于在当前或电压尖峰之后将信息恢复到其初始状态的电路，其使用存储在另一节点中的信息来修改对中的一个节点中的信息。 单元中每对的数据存储节点在限定存储单元的边界的衬底的区域内相互注入相对导电类型的相对侧。

公开(公告)号：US07868517B2

公开(公告)日：2011-01-11

申请号：US12255426

申请日：2008-10-21

Applicant: Didier Belot ,  Andreia Cathelin ,  Alexandre Augusto Shirakawa ,  Jean-Marie Pham ,  Pierre Jary ,  Eric Kerherve

Inventor： Didier Belot ,  Andreia Cathelin ,  Alexandre Augusto Shirakawa ,  Jean-Marie Pham ,  Pierre Jary ,  Eric Kerherve

IPC: H01L41/04

CPC classification number: H03H9/17 ,  H03H9/02228

Abstract: A Lamb wave resonator includes a piezoelectric layer, and a first electrode against a first face of the piezoelectric layer. The first electrode includes fingers and a contact arm, with each finger including a first side in contact with the contact arm and two other sides parallel to one another. Portions of the piezoelectric layer are at least partially etched between the two fingers to form a recess. The fingers are spaced apart from one another by a distance W calculated according to the following equation: W = n · va lateral f , with ⁢ ⁢ n ∈ N where, valateral is an acoustic propagation speed of Lamb waves, n is an order of a resonance mode of the Lamb waves, f is a resonance frequency of the Lamb wave resonator.

Abstract translation: 兰姆波谐振器包括压电层和抵靠压电层的第一面的第一电极。 第一电极包括指状物和接触臂，每个指状物包括与接触臂接触的第一侧和彼此平行的两个另外的边。 在两个手指之间至少部分蚀刻压电层的一部分以形成凹部。 手指按照以下等式计算的距离W彼此间隔开：W = n·va横向f，其中n n为N，其中，侧向是兰姆波的声传播速度，n是 Lamb波的谐振模式，f是兰姆波谐振器的谐振频率。

公开(公告)号：US07868392B2

公开(公告)日：2011-01-11

申请号：US11172609

申请日：2005-06-30

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: H01L29/76

CPC classification number: H01L27/0921 ,  H01L21/8238

Abstract: Integrated circuit comprising doped zones (3 to 8) formed in a substrate (1, 2), forming a parasitic thyristor structure with two parasitic bipolar transistors (T1, T2), the integrated circuit comprising two metallizations (16, 19) interconnecting each of the two corresponding doped zones (4, 5; 6, 7) of the integrated circuit, to reduce the base resistances (RP−, RP−) of the two bipolar transistors, at least one of the metallizations (16, 19) performed to reduce the base resistances (RN−, RP−) of the two bipolar transistors, being connected to a power supply metallization (15, 16) in the integrated circuit, entirely through the substrate (1, 2).

Abstract translation: 集成电路，包括形成在衬底（1,2）中的掺杂区（3至8），形成具有两个寄生双极晶体管（T1，T2）的寄生晶闸管结构，所述集成电路包括两个互连的金属化（16,19） 集成电路的两个对应的掺杂区域（4,5,6,7），以便降低两个双极晶体管的基极电阻（RN-，RP-），至少一个金属化层（16,19）被执行到 将两个双极晶体管的基极电阻（RN-，RP-）整体通过衬底（1,2）连接到集成电路中的电源金属化（15,16）。