公开(公告)号：US20240321350A1

公开(公告)日：2024-09-26

申请号：US18734724

申请日：2024-06-05

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Murong Lang ,  Zhenming Zhou

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C11/5678

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a cross-point memory array includes memory cells. A media controller reads one or more first memory cells and determines a read status. The read status indicates an error when reading the first memory cells. In response to this error, the controller refreshes the first memory cells. The controller uses the read status to determine zero-to-one failures associated with the first memory cells. If a number of these failures exceeds a threshold, then a refresh is applied to neighboring memory cells of the first memory cells. The physical addresses for the neighboring memory cells are determined by the controller from the physical addresses for the first memory cells.

公开(公告)号：US20240321329A1

公开(公告)日：2024-09-26

申请号：US18680550

申请日：2024-05-31

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim

IPC: G11C7/10 ,  G11C29/46

CPC classification number: G11C7/1063 ,  G11C7/1066 ,  G11C7/1096 ,  G11C29/46

Abstract: Methods, systems, and devices for selective access for grouped memory dies are described. A memory device may be configured with a select die access protocol for a group of memory dies that share a same channel. The protocol may be enabled by one or more commands from the host device, which may be communicated to each of the memory dies of the group via the channel. The command(s) may indicate a first set of one or more memory dies of the group for which a set of commands may be enabled and may also indicate a second set of one or more memory dies of the group for which at least a subset of the set of commands is disabled. When the select die access mode is enabled, the disabled memory dies may be restricted from performing the subset of commands received via the channel.

公开(公告)号：US20240321327A1

公开(公告)日：2024-09-26

申请号：US18677609

申请日：2024-05-29

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Ramachandra Rao Jogu

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/109

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a first n-type transistor having a first gate and a second n-type transistor having a second gate, and pre-decoder circuitry configured to provide a bias condition for the first gate and second gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises: a positive voltage for the first gate and a negative voltage for the second gate for a positive configuration for the memory cells, and zero volts for the first gate and the negative voltage for the second gate for a negative configuration for the memory cells.

公开(公告)号：US20240320144A1

公开(公告)日：2024-09-26

申请号：US18595703

申请日：2024-03-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Goda ,  Koichi Kawai ,  Huai-Yuan Tseng ,  Yoshihiko Kamata

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: Memories might include a controller configured to cause the memory to apply a programming pulse to a memory cell, perform an analog verify phase on the memory cell, in response to the analog verify phase, apply a first voltage level to a corresponding data line of the memory cell that is selected from a group consisting of an inhibit voltage level, a full enable voltage level, and an analog enable voltage level, apply a subsequent programming pulse to the memory cell, perform a digital verify phase on the memory cell, in response to the digital verify phase, apply a second voltage level to the corresponding data line of the memory cell that is selected from a group consisting of the inhibit voltage level and a digital enable voltage level, and apply a next subsequent programming pulse to the memory cell.

公开(公告)号：US20240320143A1

公开(公告)日：2024-09-26

申请号：US18583795

申请日：2024-02-21

Applicant: Micron Technology, Inc.

Inventor： Hui Ye

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: Memory systems and devices (and associated methods) with improved active performance loss (APL) completion detection are described herein. In one embodiment, a memory device comprises nonvolatile memory and logic configured to (i) write a first value to a first location in the nonvolatile memory, (ii) detect a power loss event corresponding to the memory device, and (iii) before powering down the memory device based at least in part on the detected power loss event, write a second value to a second location in the nonvolatile memory different from the first location. The first value and/or the second value can correspond to a current power cycle number of the memory device. After power is subsequently restored to the memory device, the logic can compare the first and second values and proceed with reconstructing the memory device using APL management data when the first value matches the second value.

公开(公告)号：US20240320093A1

公开(公告)日：2024-09-26

申请号：US18680470

申请日：2024-05-31

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm ,  Scott D. Van De Graaff ,  Mark D. Ingram ,  Todd Jackson Plum

IPC: G06F11/10 ,  G06F9/30 ,  G06F11/07 ,  G06F11/30

CPC classification number: G06F11/1068 ,  G06F9/30189 ,  G06F11/0772 ,  G06F11/3051

Abstract: Methods, systems, and devices for evaluation of memory device health monitoring logic are described. For example, a memory device may include health monitoring logic operable to activate certain internal health monitors of a set of multiple monitors and to communicate an output associated with the activated monitors. In a first mode of operation, the health monitoring logic may provide a single output that is generated from multiple outputs of the set of monitors. In a second mode of operation, the health monitoring logic may cycle through certain monitors (e.g., in a test mode), and may generate an output corresponding to respective active monitors as it cycles through the set of monitors. The health monitoring logic may communicate an output specific to each monitor to a host device such that the host device may evaluate an output from each monitor of the set of monitors.

公开(公告)号：US20240320090A1

公开(公告)日：2024-09-26

申请号：US18611423

申请日：2024-03-20

Applicant: Micron Technology, Inc.

Inventor： Febin Sunny ,  Poorna Kale ,  Saideep Tiku

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: Apparatuses and methods related to error correction via artificial intelligence (AI) are described. An augmented reality (AR) display can be coupled to a memory device. AI circuitry coupled to the memory device can receive an error correction model. Prior to receipt of the error correction model by the AI circuitry, the error correction model can be trained, externally to the memory device and AI circuitry, to correct random errors introduced to execution of the AR AI workload in hazardous conditions. The AI circuitry can execute the model to perform error correction in association with execution of the AR AI workload.

公开(公告)号：US20240319912A1

公开(公告)日：2024-09-26

申请号：US18733495

申请日：2024-06-04

Applicant: Micron Technology, Inc.

Inventor： David Matthew Springberg

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0676 ,  G06F3/0679

Abstract: Various embodiments enable a memory sub-system to perform a read operation based on consolidated memory region description data, which can be generated based on a memory region description data (e.g., SGL) provided by a host system for the read operation.

公开(公告)号：US20240319881A1

公开(公告)日：2024-09-26

申请号：US18662940

申请日：2024-05-13

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Ching-Huang Lu ,  Murong Lang

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0679

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that the wordline is disposed on a first deck of the memory deck; responsive to determining that the wordline is disposed on the first deck, determining that the wordline is associated with a first group of wordlines associated with the first deck; and responsive to determining that the wordline is associated with the first group of wordlines associated with the first deck, performing the memory access operation on the set of cells connected to the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the first group of wordlines associated with the first deck.

公开(公告)号：US20240319880A1

公开(公告)日：2024-09-26

申请号：US18598712

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Rohit SEHGAL ,  Vishal TANNA ,  Krishna SIDDHAREDDY ,  Eishan MIRAKHUR

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673

Abstract: Provided is a system comprising a first interface configured to receive first data from an external computing device, non-volatile memory operatively coupled to the first interface, and a second interface configured to communicate with a host computing device. The system also includes dynamic random-access memory (DRAM) operatively coupled to the second interface, a memory controller operatively coupled to the second interface and the DRAM and configured to control a transfer of information between the DRAM and the host computing device through the second interface, and processing circuitry at least configured to store the first data received through the first interface in the non-volatile memory.