公开(公告)号：US20100097093A1

公开(公告)日：2010-04-22

申请号：US12579951

申请日：2009-10-15

Applicant: Nicolas Ricard ,  Laurent Jean Garcia

Inventor： Nicolas Ricard ,  Laurent Jean Garcia

IPC: H03K17/687

CPC classification number: G05F1/567 ,  H03F1/56

Abstract: Circuitry including an output circuit having a first variable resistance block coupled between a first supply voltage and an output node, the first variable resistance block having a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the output node, the output circuit having an output impedance determined by the resistance of the first variable resistance block; and a compensation circuit for regulating the impedance of the first variable resistance block of the output circuit, the compensation circuit having a second variable resistance block coupled between the first supply voltage and the first node of an external resistor, the second node of the external resistor being coupled to a second supply voltage, wherein the second variable resistance block comprises a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the first node of the external resistor, and wherein the plurality of selectable resistive elements of the first and second variable resistance blocks are selected based on a voltage level at the first node of the external resistor.

Abstract translation: 电路包括具有耦合在第一电源电压和输出节点之间的第一可变电阻块的输出电路，所述第一可变电阻块具有与所述第一电源电压和所述输出之间的至少一个电阻器串联耦合的多个可选择的电阻元件 所述输出电路具有由所述第一可变电阻块的电阻确定的输出阻抗; 以及用于调节输出电路的第一可变电阻块的阻抗的补偿电路，所述补偿电路具有耦合在第一电源电压和外部电阻器的第一节点之间的第二可变电阻块，外部电阻器的第二节点 耦合到第二电源电压，其中所述第二可变电阻块包括与所述第一电源电压和所述外部电阻器的所述第一节点之间的至少一个电阻器串联耦合的多个可选择的电阻元件，并且其中所述多个可选择的电阻 基于外部电阻器的第一节点处的电压电平来选择第一和第二可变电阻块的元件。

公开(公告)号：US07701047B2

公开(公告)日：2010-04-20

申请号：US11726353

申请日：2007-03-19

Applicant: Olivier Le Briz ,  Sébastien Marsanne ,  Laurence Martin ,  Guiseppe Croce

Inventor： Olivier Le Briz ,  Sébastien Marsanne ,  Laurence Martin ,  Guiseppe Croce

IPC: H01L23/48 ,  H05K3/40

CPC classification number: H01L24/13 ,  H01L21/76897 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014

Abstract: An integrated-circuit chip includes a first electrical connection are placed on an underlying layer and covered with an intermediate dielectric layer. A second electrical connection is placed on the intermediate dielectric layer and is covered with a superficial dielectric layer. External electrical connection pads are placed on the superficial dielectric layer and extend selectively over the first electrical connection. Vias pass through the superficial dielectric layer and the intermediate dielectric layer to make connection between the first electrical connection and the external electrical connection pads.

Abstract translation: 集成电路芯片包括第一电连接被放置在下层并且被中间介电层覆盖。 第二电连接被放置在中间电介质层上并被表面电介质层覆盖。 外部电连接焊盘放置在表面电介质层上并选择性地延伸到第一电连接上。 通孔穿过表面电介质层和中间介质层，以在第一电连接和外部电连接焊盘之间形成连接。

公开(公告)号：US07700981B2

公开(公告)日：2010-04-20

申请号：US11407681

申请日：2006-04-20

Applicant: Ludovic Goux ,  Monique Gervais

Inventor： Ludovic Goux ,  Monique Gervais

IPC: H01L29/76

CPC classification number: H01L28/55 ,  H01L28/60

Abstract: The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate.

Abstract translation: 使用导电二维钙钛矿作为硅，金属或非晶氧化物衬底之间的界面和通过外延沉积的绝缘钙钛矿，以及集成电路及其制造方法，其包括通过外延沉积的绝缘钙钛矿层以形成 电容元件的电介质至少具有由导电二维钙钛矿形成的电极，其形成在所述电介质和下面的硅，金属或非晶氧化物衬底之间的界面。

公开(公告)号：US20100078673A1

公开(公告)日：2010-04-01

申请号：US12632641

申请日：2009-12-07

Applicant: Jean-Luc Morand

Inventor： Jean-Luc Morand

IPC: H01L27/06 ,  H01L29/861 ,  H01L29/72 ,  H01L29/74

CPC classification number: H01L29/417 ,  H01L29/73 ,  H01L29/739 ,  H01L29/74 ,  H01L29/861

Abstract: A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.

Abstract translation: 一种半导体部件，其中有源接合部基本上横跨其整个厚度垂直于半导体芯片的表面延伸。 与要连接的区域的触点由导电指状物提供，其基本上与要建立触点的整个区域交叉。

公开(公告)号：USRE41179E1

公开(公告)日：2010-03-30

申请号：US10209597

申请日：2002-07-30

Applicant: Philippe Monnier

Inventor： Philippe Monnier

IPC: H04N7/12

CPC classification number: H04N7/52 ,  H04N19/61 ,  H04N19/70

Abstract: A device for extracting parameters for decoding a video data flow, contained in headers preceded by a starting code of series of data coded according to an MPEG standard, organized, independently and according to the starting code, and storage of the parameters in three register banks.

Abstract translation: 一种用于提取用于对视频数据流进行解码的参数的装置，其包含在由根据MPEG标准编码的一系列数据的起始码之前的标题中，独立地并根据起始码组织，并将参数存储在三个寄存器组中 。

公开(公告)号：US07687833B2

公开(公告)日：2010-03-30

申请号：US11807491

申请日：2007-05-29

Applicant: Michel Marty ,  Jean-Christophe Giraudin ,  Philippe Coronel

Inventor： Michel Marty ,  Jean-Christophe Giraudin ,  Philippe Coronel

IPC: H01L27/00

CPC classification number: H03H9/0547

Abstract: A monolithic assembly of electronic components including a semiconductor substrate, at a first level above the substrate, at least one bulk acoustic wave resonator, at a second level above the resonator, a single-crystal semiconductor layer in which are formed semiconductor components, and recesses under the semiconductor layer portions arranged above the resonators.

Abstract translation: 包括半导体衬底的电子部件的单体组件包括在衬底上方的第一级，在谐振器上方的第二级上的至少一个体声波谐振器，形成半导体部件的单晶半导体层，以及凹部 在布置在谐振器上方的半导体层部分下方。

公开(公告)号：US07685502B2

公开(公告)日：2010-03-23

申请号：US11158516

申请日：2005-06-22

Applicant: Pascal Urard ,  Laurent Paumier

Inventor： Pascal Urard ,  Laurent Paumier

IPC: H03M13/00 ,  H03M13/03

CPC classification number: H03M13/1137 ,  H03M13/1105

Abstract: An LDPC decoder has a determined number of processing units operating in parallel. Storage circuitry contains first words having a juxtaposition of a first type of message. The storage circuitry also contains second words having a juxtaposition of a second type of message. A message provision unit provides each processing unit with the messages. A message write unit may write words into the storage circuitry in a way that depends on the contents of the words. The message provision unit may provide data in a way that depends on the contents of the words.

Abstract translation: LDPC解码器具有确定数量的并行操作的处理单元。 存储电路包含具有第一类型消息并置的第一个字。 存储电路还包含具有第二类型消息并置的第二字。 消息提供单元向每个处理单元提供消息。 消息写入单元可以以取决于单词的内容的方式将字写入存储电路。 消息提供单元可以以取决于单词的内容的方式提供数据。

公开(公告)号：US20100066472A1

公开(公告)日：2010-03-18

申请号：US12312422

申请日：2007-11-30

Applicant: Bastien Orlando ,  Bernard Viala

Inventor： Bastien Orlando ,  Bernard Viala

IPC: H01F5/00

CPC classification number: H01F17/0033 ,  H01F27/34 ,  H01F2017/0073

Abstract: The inductive micro-device comprises a rectilinear solenoid winding comprising a plurality of disjointed rectangular turns each having predetermined dimensions. At least one of the dimensions of the turns is variable and is determined individually for each turn according to the position of the turn along the winding and to predetermined magnetic characteristics of the winding, in particular a homogeneous magnetic field and/or an optimum quality factor. Said variable dimension of the turns is chosen from the width, length, thickness, height of turn and the value of the gap between two adjacent turns.

Abstract translation: 感应微型装置包括直线电磁线圈，其包括多个具有预定尺寸的不相交的矩形匝。 匝的尺寸中的至少一个是可变的，并且根据沿着绕组的匝的位置以及绕组的预定的磁特性，特别是均匀的磁场和/或最佳品质因数 。 所述匝的所述可变尺寸选自宽度，长度，厚度，转弯高度和两个相邻匝间间隙的值。

公开(公告)号：US20100044886A1

公开(公告)日：2010-02-25

申请号：US12539542

申请日：2009-08-11

Applicant: Eric Sabouret ,  Laurent Hoareau ,  Yves Salmon

Inventor： Eric Sabouret ,  Laurent Hoareau ,  Yves Salmon

IPC: H01L23/48

CPC classification number: H01L22/34 ,  H01L24/06 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/4943 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/45099

Abstract: An integrated-circuit semiconductor device includes external electrical connection pads on one face and electrical connection vias under said pads. The electrical connection vias are arranged with a defined pitch in a defined direction. Each via is respectively associated with one of a plurality of adjacent zones of the face. These zones extend perpendicularly to the pitch direction. The electrical connection pads are grouped in adjacent pairs. An insulation space is located between the pads of each pair of electrical connection pads. In a direction perpendicular to the pitch direction, the pads in the pair are spaced apart. The pads of each pair of electrical connection pads extend over a pair of adjacent zones and are associated with two adjacent vias.

Abstract translation: 集成电路半导体器件包括在一个面上的外部电连接焊盘和在所述焊盘之下的电连接通孔。 电连接通孔以确定的方向以限定的间距布置。 每个通孔分别与面部的多个相邻区域中的一个相关联。 这些区域垂直于俯仰方向延伸。 电连接垫被分组成相邻的对。 绝缘空间位于每对电连接焊盘的焊盘之间。 在垂直于俯仰方向的方向上，该对中的焊盘间隔开。 每对电连接焊盘的焊盘在一对相邻的区域上延伸并且与两个相邻的通孔相关联。

公开(公告)号：US07667292B2

公开(公告)日：2010-02-23

申请号：US11415393

申请日：2006-05-01

Applicant: Jean-Christophe Giraudin ,  Vincent Fiori ,  Philippe Delpech

Inventor： Jean-Christophe Giraudin ,  Vincent Fiori ,  Philippe Delpech

IPC: H01L27/08

CPC classification number: H01L29/66181 ,  H01L21/31612 ,  H01L21/31633 ,  H01L27/0805 ,  H01L28/91

Abstract: An integrated circuit includes at least one capacitor that is formed on a layer provided with at least one first trench. The capacitor, which is provided with a dielectric layer that separates two electrodes, conforms to the shape of the first trench, but leaves a part of the first trench unfilled. A material capable of absorbing stresses associated with the displacements of the walls of the trench is placed in the trench to fill the part of the first trench. A second trench is formed at least partly surrounding the first trench. This second trench is also at least partly filled with a material capable of absorbing stresses associated with the displacements of the walls of the second trench. A void may be included in the stress absorbing material which fills either of the first or second trenches.

Abstract translation: 集成电路包括至少一个形成在设置有至少一个第一沟槽的层上的电容器。 设置有分隔两个电极的电介质层的电容器符合第一沟槽的形状，但是留下未填充的第一沟槽的一部分。 能够吸收与沟槽的壁的位移相关联的应力的材料被放置在沟槽中以填充第一沟槽的一部分。 至少部分地围绕第一沟槽形成第二沟槽。 该第二沟槽还至少部分地填充有能够吸收与第二沟槽的壁的位移相关联的应力的材料。 在应力吸收材料中可以包含空隙，填充第一或第二沟槽中的任一个。