公开(公告)号：US20210342285A1

公开(公告)日：2021-11-04

申请号：US16863149

申请日：2020-04-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SeyedMohammad SEYEDZADEHDELCHEH ,  Steven RAASCH ,  Sergey BLAGODUROV

IPC: G06F13/40 ,  H03M7/30 ,  G06F13/42

Abstract: Data are serially communicated over an interconnect between an encoder and a decoder. The encoder includes a first training unit to count a frequency of symbol values in symbol blocks of a set of N number of symbol blocks in an epoch. A circular shift unit of the encoder stores a set of most-recently-used (MRU) amplitude values. An XOR unit is coupled to the first training unit and the first circular shift unit as inputs and to the interconnect as output. A transmitter is coupled to the encoder XOR unit and the interconnect and thereby contemporaneously sends symbols and trains on the symbols. In a system, a device includes a receiver and decoder that receive, from the encoder, symbols over the interconnect. The decoder includes its own training unit for decoding the transmitted symbols.

公开(公告)号：US11158106B2

公开(公告)日：2021-10-26

申请号：US16723969

申请日：2019-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Vineet Goel ,  Pazhani Pillai ,  Ruijin Wu ,  Christopher J. Brennan ,  Andrew S. Pomianowski

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60

Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data, and writing a VRS rate feedback buffer based on the updated VRS data.

公开(公告)号：US20210326063A1

公开(公告)日：2021-10-21

申请号：US16848920

申请日：2020-04-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ANIRBAN NAG ,  NUWAN JAYASENA ,  SHAIZEEN AGA

IPC: G06F3/06 ,  G06F9/448 ,  G06F9/48

Abstract: Memory operations using compound memory commands, including: receiving, by a memory module, a compound memory command indicating one or more operations to be applied to each portion of a plurality of portions of contiguous memory in the memory module; generating, based on the compound memory command, a plurality of memory commands to apply the one or more operations to each portion of the plurality of portions of contiguous memory; and executing the plurality of memory commands.

公开(公告)号：US11151075B2

公开(公告)日：2021-10-19

申请号：US16221181

申请日：2018-12-14

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gordon Caruk ,  Gerald R. Talbot

IPC: G06F13/42 ,  G06F13/12 ,  G06F13/40

Abstract: An interconnect controller includes a data link layer controller coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from and sends data packets to the transaction layer, and a physical layer controller coupled to the data link layer controller and to a communication link. The physical layer controller selectively operates at a first predetermined link speed. The physical layer controller has an enhanced speed mode, wherein in response to performing a link initialization, the interconnect controller queries a data processing platform to determine whether the enhanced speed mode is permitted, performs at least one setup operation to select an enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed, and subsequently operates the communication link using the enhanced speed.

公开(公告)号：US20210318862A1

公开(公告)日：2021-10-14

申请号：US16848681

申请日：2020-04-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Srinivasan Subramanian ,  Pruthvi K. Madugundu ,  Freddy Paul ,  Jagadish Krishnamoorthy ,  Diwakar Das ,  Praveen K. Jain

IPC: G06F8/71 ,  G06F9/445 ,  G06F16/176 ,  G06F16/14

Abstract: An electronic device includes a processor and a storage device having a file system with a plurality of directories. The processor executes an application that has a dependency on a shared library, the shared library having a dependency on a runtime component. When executing the application, the processor loads the shared library, the loading including executing a constructor for the shared library. Executing the constructor causes the processor to identify a selected directory where a compatible version of the runtime component is to be found based on a location of the shared library in the file system, the location of the shared library being determined from an application context from the application. When subsequently loading the runtime component for execution, the processor locates the runtime component in the selected directory.

公开(公告)号：US11144324B2

公开(公告)日：2021-10-12

申请号：US16586642

申请日：2019-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew T. Sobel ,  Joshua James Lindner ,  Neil N. Marketkar ,  Kai Troester ,  Emil Talpes ,  Ashok Tirupathy Venkatachar

IPC: G06F9/38

Abstract: Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.

公开(公告)号：US11143700B2

公开(公告)日：2021-10-12

申请号：US16582758

申请日：2019-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Venkat Krishnan Ravikumar ,  Nathan Linarto ,  Wen Tsann Lua ,  Abel Tan Yew Hong ,  Shei Lay Phoa ,  Gopinath Ranganathan ,  Jiann Minn Chin

IPC: G01R31/28 ,  G01R31/265 ,  G01R31/311 ,  G01R31/01 ,  G01R23/17 ,  G01R29/08

Abstract: An optic probe is used to measure signals from a device under test. The optic probe is positioned at a target probe location within a cell of the device under test, the cell including a target net to be measured and a plurality of non-target nets. A test pattern is applied to the cell with the optic probe a laser probe (LP) waveform is obtained in response. A target net waveform is extracted from the LP waveform by: (i) simulating a combinational logic analysis (CLA) cross-talk waveform to model cross-talk from selected non-target nets by simulating an optical response of the cell to the test pattern with the target net masked; (ii) estimating a cross-talk weight; and (iii) determining a target net waveform by weighting the CLA cross-talk waveform according to the cross-talk weight and subtracting the weighted CLA cross-talk waveform from the LP waveform.

公开(公告)号：US11140107B2

公开(公告)日：2021-10-05

申请号：US15418369

申请日：2017-01-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Andrew G. Kegel ,  Arkaprava Basu

IPC: G06F15/16 ,  H04L12/58 ,  G06Q10/10 ,  G06F15/173

Abstract: Various messaging systems and methods are disclosed for meeting invitation management. In one aspect, a method of messaging is provided that includes generating a message to invite one or more invitees to a meeting. The message includes an assertion to suppress an auto-responder of the one or more invitees. The message is sent to the one or more invitees. The assertion suppresses the auto-responder of the one or more invitees.

公开(公告)号：US20210304486A1

公开(公告)日：2021-09-30

申请号：US17346903

申请日：2021-06-14

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ruijin Wu ,  Skyler Jonathon Saleh ,  Christopher J. Brennan ,  Kei Ming Kwong ,  Anthony Hung-Cheong Chan

IPC: G06T15/00 ,  G06T9/00 ,  G06T7/90

Abstract: A technique for compressing an original image is disclosed. According to the technique, an original image is obtained and a delta-encoded image is generated based on the original image. Next, a segregated image is generated based on the delta-encoded image and then the segregated image is compressed to produce a compressed image. The segregated image is generated because the segregated image may be compressed more efficiently than the original image and the delta image.

公开(公告)号：US11132204B2

公开(公告)日：2021-09-28

申请号：US16721421

申请日：2019-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rex Eldon McCrary

IPC: G06F3/06 ,  G06F9/48 ,  G06F9/38

Abstract: A processing system includes a set of queues to store command buffers prior to execution in a corresponding plurality of pipelines. The processing system also includes one or more first doorbells and a second doorbell. The first doorbells map to one or more queues in the set of queues on a one-to-one basis. The second doorbell maps to a subset of the set of queues on a one-to-many basis. A doorbell monitor generates an interrupt in response to an empty queue in the subset becoming a non-empty queue. A scheduler polls the subset in response to the interrupt. The scheduler schedules a command buffer from the non-empty queue for execution or adds the command buffer to a pool for subsequent execution.