公开(公告)号：US06566212B1

公开(公告)日：2003-05-20

申请号：US09761953

申请日：2001-01-17

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L29/6656

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a solid-phase impurity source. The solid-phase impurity source can be a doped silicon dioxide layer approximately 300 nm thick. The structure is thermally annealed to drive dopants from the solid-phase impurity source into the source and drain regions. The dopants from the impurity source provide ultra-shallow source and drain extensions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法利用固相杂质源。 固相杂质源可以是约300nm厚的掺杂二氧化硅层。 该结构被热退火以将来自固相杂质源的掺杂剂驱动到源区和漏区。 来自杂质源的掺杂剂提供超浅源极和漏极延伸。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06559015B1

公开(公告)日：2003-05-06

申请号：US09873169

申请日：2001-06-01

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  Y10S977/832

Abstract: For fabricating a field effect transistor on an active device area of a semiconductor substrate, a gate dielectric and a gate electrode are formed on a portion of the active device area. First spacers are formed on sidewalls of the gate electrode and the gate dielectric. A contact dopant is implanted into exposed regions of the active device area to form drain and source contact junctions. A contact laser thermal anneal is performed to activate the contact dopant within the drain and source contact junctions. The first spacers are removed, and an extension dopant is implanted into exposed regions of the active device area to form drain and source extension junctions. An extension laser thermal anneal is performed to activate the extension dopant within the drain and source extension junctions. The fluence of the extension laser thermal anneal is lower than the fluence of the contact laser thermal anneal.

Abstract translation: 为了在半导体衬底的有源器件区域上制造场效应晶体管，在有源器件区域的一部分上形成栅极电介质和栅电极。 在栅极电极和栅极电介质的侧壁上形成第一间隔物。 将接触掺杂剂注入到有源器件区域的暴露区域中以形成漏极和源极接触结。 进行接触激光热退火以激活漏极和源极接触接点内的接触掺杂剂。 去除第一间隔物，并且将延伸掺杂剂注入到有源器件区域的暴露区域中以形成漏极和源极延伸结。 执行延伸激光热退火以激活漏极和源极延伸结中的延伸掺杂剂。 扩展激光热退火的能量密度低于接触激光热退火的能量密度。

公开(公告)号：US06552377B1

公开(公告)日：2003-04-22

申请号：US09533610

申请日：2000-03-22

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2972

CPC classification number: H01L21/82345

Abstract: A method for making a ULSI MOSFET includes depositing a high-k gate insulator on a silicon substrate and then depositing a field oxide layer over the gate insulator. The field oxide layer is masked with photoresist and the photoresist patterned to establish first gate windows, and the oxide below the windows is then etched away to establish first gate voids in the oxide. The first gate voids are filled with a first metallic gate electrode material that is suitable for establishing a gate electrode of, e.g., an N-channel MOSFET. Second gate voids are similarly made in the oxide and filled with a second gate electrode material that is suitable for establishing a gate electrode of, e.g., an P-channel MOSFET or another N-channel MOSFET having a different threshold voltage than the first MOSFET. With this structure, plural threshold design voltages are supported in a single ULSI chip that uses high-k gate insulator technology.

Abstract translation: 制造ULSI MOSFET的方法包括在硅衬底上沉积高k栅极绝缘体，然后在栅极绝缘体上沉积场氧​​化物层。 用光致抗蚀剂掩蔽场氧化物层，并且将光致抗蚀剂图案化以建立第一栅极窗口，然后蚀刻掉窗口下面的氧化物以在氧化物中建立第一栅极空隙。 第一栅极空隙填充有适于建立例如N沟道MOSFET的栅电极的第一金属栅电极材料。 第二栅极空隙类似地在氧化物中制成并且填充有适于建立例如P沟道MOSFET或具有不同于第一MOSFET的阈值电压的另一N沟道MOSFET的栅电极的第二栅电极材料。 利用这种结构，在使用高k栅极绝缘体技术的单个ULSI芯片中支持多个阈值设计电压。

公开(公告)号：US06534373B1

公开(公告)日：2003-03-18

申请号：US09817919

申请日：2001-03-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21331

CPC classification number: H01L29/66772 ,  H01L21/26586 ,  H01L29/66659 ,  H01L29/78612 ,  H01L29/78624

Abstract: A method of fabricating an integrated circuit utilizes asymmetric source/drain junctions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS). The drain extension is deeper than the source extension. The source extension is more conductive than the drain extension. The transistor has reduced short channel effects and strong drive current and yet is reliable.

Abstract translation: 一种制造集成电路的方法利用不对称的源极/漏极结。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。 漏极扩展比源扩展更深。 源极延伸比漏极延伸更为导电。 晶体管减少了短沟道效应和强大的驱动电流，而且可靠。

公开(公告)号：US06509253B1

公开(公告)日：2003-01-21

申请号：US09785680

申请日：2001-02-16

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L213205

CPC classification number: H01L29/6653 ,  H01L21/28052 ,  H01L21/28114

Abstract: An integrated circuit includes a transistor with a T-shaped gate conductor. The T-shaped gate conductor can achieve a lower sheet resistance characteristic. The transistor can include a silicided source region, a silicided drain region, and a gate structure having the T-shaped gate conductor. The T-shaped gate conductor has a silicided top portion. The silicided top portion can have different silicidation characteristics than the silicided source region and the silicided drain region.

Abstract translation: 集成电路包括具有T形栅极导体的晶体管。 T形栅极导体可以实现较低的薄层电阻特性。 晶体管可以包括硅化源极区，硅化漏极区和具有T形栅极导体的栅极结构。 T形栅极导体具有硅化顶部。 硅化顶部可以具有与硅化物源区和硅化物漏极区不同的硅化特性。

公开(公告)号：US06503817B1

公开(公告)日：2003-01-07

申请号：US09405519

申请日：1999-09-23

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21425

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324

Abstract: A method for suppressing silicidation retardation effects caused by high dopant concentrations, in particular high Arsenic concentrations, at the surface of a semiconductor substrate. The method includes implanting a preamorphization substance into the substrate to define the boundary of the source/drain, then implanting the dopant at high energy to establish a dopant concentration peak that is distanced from the surface of the substrate. The dopant is activated by rapid thermal annealing, with the relatively deep dopant concentration peak facilitating subsequent improved formation of silicide on the surface of the substrate.

Abstract translation: 一种用于抑制由半导体衬底的表面上的高掺杂剂浓度，特别是高砷浓度引起的硅化延迟效应的方法。 该方法包括将预变质物质注入到衬底中以限定源极/漏极的边界，然后以高能量注入掺杂剂以建立与衬底表面相隔的掺​​杂剂浓度峰。 通过快速热退火激活掺杂剂，掺杂浓度相对较高的峰有利于随后在衬底的表面上形成硅化物。

公开(公告)号：US06495437B1

公开(公告)日：2002-12-17

申请号：US09781039

申请日：2001-02-09

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L213205

CPC classification number: H01L21/28194 ,  H01L21/28238 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of forming a dielectric gate insulator in a transistor is disclosed herein. The method includes providing a gate structure including a layer of material over a semiconductor structure, siliciding the substrate, and transforming the layer of material into a gate dielectric material. The gate dielectric material can be a high-k gate dielectric material.

Abstract translation: 本文公开了在晶体管中形成电介质栅极绝缘体的方法。 该方法包括在半导体结构上提供包括一层材料的栅极结构，硅化硅衬底，以及将该材料层转变成栅极电介质材料。 栅介质材料可以是高k栅介质材料。

公开(公告)号：US06479358B1

公开(公告)日：2002-11-12

申请号：US09773829

申请日：2001-01-31

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21331

CPC classification number: H01L29/66628 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28518 ,  H01L29/665

Abstract: A MOSFET with raised source/drains that can readily be silicidated and have shallow source/drain extensions. The invention uses chemical vapor epitaxy to create raised source/drains. The invention provides molecules containing silicon and molecules containing germanium, preferably GeH4, for the chemical vapor epitaxy. Initially, the concentration of GeH4 is between 5 to 10% of the concentration of molecules containing silicon. During the chemical vapor epitaxy, the concentration of GeH4 is reduced to zero. The raised source/drains and the gate are subjected to silicidation. The higher concentrations of GeH4 allow more selective epitaxy to silicon, thus preventing deposition on the polysilicon gate, nitride spacers and isolation trenches. It also allows for the use of lower epitaxy temperatures reducing movements of dopants in the source/drain extension. The slow reduction in concentration of GeH4 allows for the epitaxy temperature to be kept low. The reduced germanium concentration near the end of the epitaxy allows better silicidation of the raised source/drain.

Abstract translation: 具有升高的源极/漏极的MOSFET，其可以容易地被硅化并具有浅的源极/漏极延伸。 本发明使用化学气相外延来产生升高的源/排水。 本发明提供含有硅的分子和含锗的分子，优选为GeH 4，用于化学气相外延。 最初，GeH 4的浓度为含硅分子浓度的5至10％。 在化学气相外延期间，GeH4的浓度降低到零。 升高的源极/漏极和栅极经受硅化。 较高浓度的GeH 4允许对硅进行更多的选择性外延，从而防止沉积在多晶硅栅极，氮化物间隔物和隔离沟槽上。 它还允许使用较低的外延温度降低源极/漏极延伸中的掺杂剂的移动。 GeH4浓度的缓慢降低允许外延温度保持较低。 在外延结束附近的锗浓度降低，可以使升高的源极/漏极更好的硅化。

公开(公告)号：US06465313B1

公开(公告)日：2002-10-15

申请号：US09900403

申请日：2001-07-05

Applicant: Bin Yu ,  Ralf van Bentum

Inventor： Bin Yu ,  Ralf van Bentum

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L29/78612 ,  H01L29/78621

Abstract: A semiconductor device and a method of forming same are disclosed. The device includes an SOI wafer including a semiconductor layer, a substrate and a buried insulator layer therebetween; the semiconductor layer including a source region, a drain region, and a body region disposed between the source and drain regions, the source and drain regions including respective source and extensions which extend partially laterally inwardly towards one another above the body region; and, a gate on the semiconductor layer disposed above the body region, the gate being operatively arranged with the source, drain, and body regions to form a transistor; wherein the source and drain regions include source and drain deep doped regions on opposite sides of and laterally spaced from the gate and laterally adjacent to the respective source and drain extensions, and wherein the source and drain extensions include respective source and drain silicide extension portions disposed therein of a first thickness and the source and drain deep doped regions include respective source and drain silicide deep portions disposed therein of a second thickness relatively thicker than the first thickness.

Abstract translation: 公开了一种半导体器件及其形成方法。 该器件包括：SOI晶片，其包括半导体层，衬底和掩埋绝缘体层; 所述半导体层包括源极区，漏极区和设置在所述源极和漏极区之间的主体区，所述源极和漏极区包括在所述主体区域上部分地横向向内朝向彼此延伸的相应的源极和延伸部; 以及设置在所述体区域上方的所述半导体层上的栅极，所述栅极与所述源极，漏极和主体区域可操作地布置以形成晶体管; 其中所述源极和漏极区包括在所述栅极的相对侧上并且与所述栅极横向间隔开并且横向相邻于所述源极和漏极延伸部的源极和漏极深掺杂区域，并且其中所述源极和漏极延伸部分包括相应的源极和漏极硅化物延伸部分， 其中第一厚度和源极和漏极深掺杂区域包括设置在其中的相对于比第一厚度更厚的第二厚度的源极和漏极硅化物深部分。

公开(公告)号：US06461945B1

公开(公告)日：2002-10-08

申请号：US09599270

申请日：2000-06-22

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2104

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66916 ,  H01L29/7833 ,  H01L29/802

Abstract: A method of manufacturing an integrated circuit utilizes solid phase epitaxy to form a channel region. The method includes providing an amorphous semiconductor material including germanium, crystallizing the amorphous semiconductor material via solid phase epitaxy, and doping to form a source location and a drain location. The semiconductor material containing germanium can increase the charge mobility associated with the transistor.

Abstract translation: 集成电路的制造方法利用固相外延形成沟道区。 该方法包括提供包括锗的非晶半导体材料，通过固相外延结晶非晶半导体材料，以及掺杂以形成源极位置和漏极位置。 含锗的半导体材料可以增加与晶体管相关的电荷迁移率。