公开(公告)号：US08942309B1

公开(公告)日：2015-01-27

申请号：US13863243

申请日：2013-04-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Wilson

IPC: H04L27/00 ,  H04L25/02

CPC classification number: H04L25/14

Abstract: An intermediate voltage is maintained between a first voltage and a second voltage by conditionally or selectively performing data bus inversion (DBI) and/or data swap operations on a first and second transmit channel. The operations are performed to, in some instances, create a current imbalance between the first and second channel where the intermediate voltage drifts toward a target range or target value between the first voltage and second voltage in response to the created imbalance.

Abstract translation: 通过在第一和第二发射信道上有条件地或有选择地执行数据总线反相（DBI）和/或数据交换操作来将中间电压保持在第一电压和第二电压之间。 执行这些操作以在一些情况下产生第一和第二通道之间的电流不平衡，其中中间电压响应于所产生的不平衡而偏移到目标范围或第一电压和第二电压之间的目标值。

公开(公告)号：US08929424B2

公开(公告)日：2015-01-06

申请号：US14145966

申请日：2014-01-01

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC: H04B3/46 ,  H04B17/00 ,  H04L7/00 ,  H04L7/04 ,  H04L27/00 ,  H04L7/10 ,  H04Q1/20

CPC classification number: H04B17/11 ,  H04B17/00 ,  H04B17/21 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/043 ,  H04L7/10 ,  H04L27/00

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

公开(公告)号：US20140269006A1

公开(公告)日：2014-09-18

申请号：US14210085

申请日：2014-03-13

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Gary Bela Bronner ,  Frederick A. Ware

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79

Abstract: A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node between a first terminal of the first resistive memory element and a first terminal of the second resistive memory element, and a transistor comprising a gate electrically coupled with the common node.

Abstract translation: 存储器件包括电阻存储器单元阵列。 阵列中的每个电阻性存储单元包括第一电阻性存储器元件，第二电阻性存储器元件，其与第一电阻性存储器元件电连接在第一电阻性存储器元件的第一端子与第二电阻性存储器的第一端子之间的公共节点处 元件，以及包括与公共节点电耦合的栅极的晶体管。

公开(公告)号：US20140258601A1

公开(公告)日：2014-09-11

申请号：US14280437

申请日：2014-05-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern

IPC: G06F12/02

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/60 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

Abstract translation: 存储器系统包括表现出与写入操作不对称的磨损机制的非易失性物理存储器，例如闪速存储器。 易失性存储器的相对较小的缓存减少了写入次数，并且磨损均衡存储器访问方法将写入均匀地分布在非易失性存储器上。

公开(公告)号：US20140244923A1

公开(公告)日：2014-08-28

申请号：US14267446

申请日：2014-05-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F1/10 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

Abstract translation: 时钟信号通过时钟信号线发送到第一和第二集成电路（IC）组件，该时钟信号在第一IC组件处具有第一到达时间，而在第二IC组件处具有第二较晚的到达时间。 在对应于时钟信号的转变的各个时刻，写入命令被发送到要被这些分量采样的第一和第二IC组件，并且与写命令相关联地将写数据发送到第一和第二IC组件。 第一和第二选通信号分别被发送到第一和第二IC组件，以便在这些组件中对第一和第二写入数据进行时间接收。 从多个相位偏移定时信号中选择第一和第二选通信号，以补偿时钟信号与第一和第二选通信号之间的各自的定时偏差。

公开(公告)号：US20140192940A1

公开(公告)日：2014-07-10

申请号：US14201778

申请日：2014-03-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00

CPC classification number: H04L7/0016 ,  G11C7/04 ,  G11C2207/2254 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract translation: 方法和系统提供在通信信道的正常操作期间不时地执行校准周期。 校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。 使用第二组件上的接收器从通信链路接收校准模式。 响应于所接收的校准模式来确定通信信道的参数的校准值。 校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。 对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，以及将这些校准模式重新发送回第一组件以用于调整第一组件上的通道的参数。

公开(公告)号：US20140169110A1

公开(公告)日：2014-06-19

申请号：US13899142

申请日：2013-05-21

Applicant: Rambus Inc.

Inventor： Jade M. Kizer ,  John M. Wilson ,  John Eble, III ,  Frederick A. Ware

IPC: G11C7/10

CPC classification number: G11C7/1066 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

Abstract: Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.

Abstract translation: 在存储器系统中提供同步。 在存储器写入操作期间，使用控制信号将定时参考信号发送到存储器件，并且从存储器件接收校准信号。 根据校准信号调整内部时钟信号，然后根据内部时钟发送数据信号。 以这种方式，数据被同步，使得数据根据本地时钟信号被精确地采样。

公开(公告)号：US20140140149A1

公开(公告)日：2014-05-22

申请号：US13959633

申请日：2013-08-05

Applicant: Rambus Inc.

Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC: G11C7/22 ,  G11C7/02

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/02 ,  G11C7/22

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

Abstract translation: 存储器控制器包括用于接收数据选通信号和对应的读取数据的接口。 数据选通信号和读取数据对应于由存储器控制器发出的读取命令，并且根据数据选通信号和使能信号接收读取的数据。 存储器控制器中的电路是动态地调整使能信号和数据选通信号之间的定时偏移，并且控制逻辑将根据从自由信号发出的最后读取命令以来的时间间隔的确定发出补充读取命令 存储器控制器超过预定值。

公开(公告)号：US20140047155A1

公开(公告)日：2014-02-13

申请号：US13963391

申请日：2013-08-09

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Frederick A. Ware

IPC: G06F13/40

CPC classification number: G06F13/1673 ,  G06F9/4881 ,  G06F13/1678 ,  G06F13/4059 ,  G06F2209/486 ,  G06F2209/5018 ,  G11C11/4076 ,  G11C11/4094

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

Abstract translation: 公开了一种通过具有主数据总线宽度的主数据总线在存储器控制器和至少一个存储器模块之间传送数据的方法。 该方法包括响应于来自存储器控制器的螺纹存储器请求经由对应的数据总线路径访问存储器件组中的第一个。 访问导致数据组共同形成通过对应的辅助数据总线路径传送的第一数据线程。 第一数据线程跨越主数据总线宽度的传输是在第一时间间隔内执行的，而在该第一时间间隔期间使用少于主数据传输连续吞吐量。 在第一时间间隔期间，在主数据总线上传送来自第二数据线程的至少一个数据组。

公开(公告)号：US20130346822A1

公开(公告)日：2013-12-26

申请号：US13914091

申请日：2013-06-10

Applicant: Rambus Inc.

Inventor： Jade M. Kizer ,  John Wilson ,  Lei Luo ,  Frederick A. Ware ,  Jared L. Zerbe

IPC: H03M13/47

CPC classification number: H03M13/47 ,  H04L25/4919

Abstract: Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.

Abstract translation: 描述电路的实施例。 在该电路中，接收电路包括M个输入节点，该输入节点在时间间隔期间在M个链路上接收一组M个符号，其中该M个符号集合与码字相关联。 此外，接收电路包括耦合到M个输入节点的解码器，其基于该M个符号集来确定码空间中的码字，并且将码字解码为相应的一组N个解码符号。 此外，接收电路可以包括检测器，其检测M个符号集合中的第一值的多个实例中的不平衡以及M个符号集合中的第二值的实例的数量，并且如果不平衡是 检测到，这会导致错误条件。