公开(公告)号：US06458639B1

公开(公告)日：2002-10-01

申请号：US09773828

申请日：2001-01-31

Applicant: Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

Inventor： Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

IPC: H01L2974

CPC classification number: H01L21/28194 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/981 ,  H01L2924/00

Abstract: A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.

Abstract translation: 在硅衬底上形成场效应晶体管（FET），其中氮化物栅极绝缘体层沉积在衬底上，并且氧化物栅极绝缘体层沉积在氮化物层上以使栅电极与衬底中的源极和漏极区域绝缘 。 然后去除栅极材料以建立栅极空隙，并且间隔物沉积在空隙的侧面上，使得只有一部分氧化物层被间隔物覆盖。 然后，去除氧化物层的非屏蔽部分，从而在栅极空隙下的源极和漏极延伸层之间建立氧化物层和氮化物层之间的步骤，以减少栅极和延伸部之间的后续电容耦合和电荷载流子隧道。 去除间隔物，并用栅电极材料重新填充栅极空隙。

公开(公告)号：US06445016B1

公开(公告)日：2002-09-03

申请号：US09795159

申请日：2001-02-28

Applicant: Judy Xilin An ,  Bin Yu

Inventor： Judy Xilin An ,  Bin Yu

IPC: H01L31072

CPC classification number: H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

Abstract: A silicon-on-insulator (SOI) transistor. The SOI transistor having a source and a drain having a body disposed therebetween, the source being implanted with germanium to form an area of silicon-germanium adjacent a source/body junction in a lower portion of the source, the area of silicon-germanium in the source forming a hetero junction along a lower portion of the source/body junction.

Abstract translation: 绝缘体上硅（SOI）晶体管。 具有源极和漏极的SOI晶体管具有设置在其间的主体，源被注入锗以形成邻近源极的下部的源极/主体结的硅 - 锗的区域，硅 - 锗的面积 源沿着源极/主体结的下部形成异质结。

公开(公告)号：US06432763B1

公开(公告)日：2002-08-13

申请号：US09809133

申请日：2001-03-15

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L218238

CPC classification number: H01L29/6659 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/2807 ,  H01L29/4925 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

Abstract: For fabricating a field effect transistor on a semiconductor substrate, a gate dielectric of the field effect transistor is formed on a semiconductor substrate. A doped gate electrode, which may be comprised of silicon germanium (SiGe) for example, is formed on the gate dielectric. An amorphous semiconductor structure, which may be comprised of amorphous silicon for example, is formed on the doped gate electrode. A hardmask structure comprised of a hardmask dielectric material is formed on the amorphous semiconductor structure. The gate dielectric, the doped gate electrode, the amorphous semiconductor structure, and the hardmask structure form a gate stack. Liner dielectric structures are formed on sidewalls of the gate stack. A dopant is implanted into exposed regions of the semiconductor substrate after forming the liner dielectric structures on the sidewalls of the gate stack. For example, halo dopant may be implanted at an angle toward the sidewalls of the gate stack for forming halo regions of the field effect transistor. In this manner, the liner dielectric structures on the sidewalls of the gate stack prevent bombardment of implantation ions against the sidewalls of the doped gate electrode to prevent contamination of the implantation chamber. In addition, the amorphous semiconductor structure on top of the doped gate electrode prevents out-diffusion of the germanium from the doped gate electrode since germanium substantially does not diffuse through amorphous silicon. The hardmask structure on the amorphous silicon structure prevents bombardment of implantation ions against the top of a semiconductor material of the gate stack to further prevent contamination of the implantation chamber.

Abstract translation: 为了在半导体衬底上制造场效应晶体管，在半导体衬底上形成场效应晶体管的栅极电介质。 可以在栅极电介质上形成例如可以由硅锗（SiGe）构成的掺杂栅电极。 可以在掺杂栅电极上形成例如可以由非晶硅构成的非晶半导体结构。 在非晶半导体结构上形成由硬掩模电介质材料构成的硬掩模结构。 栅极电介质，掺杂栅电极，非晶半导体结构和硬掩模结构形成栅叠层。 衬垫电介质结构形成在栅叠层的侧壁上。 在栅堆叠的侧壁上形成衬垫电介质结构后，将掺杂剂注入到半导体衬底的暴露区域中。 例如，卤素掺杂剂可以以一角度注入到栅叠层的侧壁上，以形成场效应晶体管的晕区。 以这种方式，栅叠层的侧壁上的衬垫电介质结构防止注入离子抵抗掺杂栅电极的侧壁的轰击，以防止注入腔的污染。 此外，掺杂栅电极顶部的非晶半导体结构防止了锗从掺杂栅电极的扩散，因为锗基本上不扩散通过非晶硅。 非晶硅结构上的硬掩模结构防止注入离子抵抗栅极堆叠的半导体材料的顶部的轰击，以进一步防止注入室的污染。

公开(公告)号：US06426259B1

公开(公告)日：2002-07-30

申请号：US09713754

申请日：2000-11-15

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/517 ,  H01L29/66666 ,  H01L29/7827

Abstract: For fabricating a vertical field effect transistor on a semiconductor substrate, a first layer of dielectric material is deposited on the semiconductor substrate. A layer of metal is then deposited on the first layer of dielectric material, and a second layer of dielectric material is deposited on the layer of metal. A channel opening is etched through the second layer of dielectric material, the layer of metal, and the first layer of dielectric material. A source and drain dopant is implanted through the channel opening and into the semiconductor substrate to form a drain region of the vertical field effect transistor in the semiconductor substrate. Metal oxide is then formed at any exposed surface of the layer of metal on sidewalls of the channel opening in a thermal oxidation process to form a gate dielectric of the vertical field effect transistor. The channel opening is filled with a semiconductor material, and a semiconductor structure is also grown from the semiconductor material filling the channel opening, with the semiconductor structure extending above the channel opening. The source and drain dopant is also implanted into the semiconductor structure to form a source region of the vertical field effect transistor. A thermal anneal is performed such that the drain region extends into the channel opening to be between the metal oxide at the sidewalls of the channel opening and such that the source region extends into the channel opening to be between the metal oxide at the sidewalls of the channel opening. A portion of the semiconductor material in the channel opening remains undoped without the source and drain dopant between the drain region and the source region to form a channel region of the vertical field effect transistor.

Abstract translation: 为了在半导体衬底上制造垂直场效应晶体管，在半导体衬底上沉积第一层电介质材料。 然后将一层金属沉积在第一介电材料层上，并且第二层电介质材料沉积在金属层上。 通过第二介电材料层，金属层和第一介电材料层蚀刻通道开口。 源极和漏极掺杂剂通过沟道开口注入到半导体衬底中以在半导体衬底中形成垂直场效应晶体管的漏极区。 然后在热氧化过程中在通道开口的侧壁上的金属层的任何暴露的表面上形成金属氧化物，以形成垂直场效应晶体管的栅极电介质。 沟道开口填充有半导体材料，并且半导体结构也从填充沟道开口的半导体材料生长，半导体结构在沟道开口上方延伸。 源极和漏极掺杂剂也被注入到半导体结构中以形成垂直场效应晶体管的源极区域。 进行热退火，使得漏区延伸到通道开口中，位于通道开口的侧壁处的金属氧化物之间，使得源区延伸到通道开口中，位于通道开口的侧壁处的金属氧化物之间 频道开放。 沟道开口中的半导体材料的一部分保持未掺杂，而在漏极区和源极区之间没有源极和漏极掺杂剂，以形成垂直场效应晶体管的沟道区。

公开(公告)号：US06410371B1

公开(公告)日：2002-06-25

申请号：US09794884

申请日：2001-02-26

Applicant: Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

Inventor： Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

IPC: H01L2184

CPC classification number: H01L29/66742 ,  H01L21/76256 ,  H01L29/1054 ,  H01L29/78687 ,  Y10S438/977

Abstract: A method of forming a semiconductor-on-insulator (SOI) wafer. The method includes the steps of providing a first wafer, the first wafer having a silicon substrate and an oxide layer disposed thereon; providing a second wafer, the second wafer having a silicon substrate, the substrate of the second wafer having a silicon-germanium layer disposed thereon, a silicon layer disposed on the silicon-germanium layer and an oxide layer disposed on the silicon layer; wafer bonding the first and second wafers; and removing an undesired portion of the substrate from the second wafer to form an upper silicon layer. The resulting SOI wafer structure is also disclosed.

Abstract translation: 一种形成绝缘体上半导体（SOI）晶片的方法。 该方法包括提供第一晶片，第一晶片具有硅衬底和设置在其上的氧化物层的步骤; 提供第二晶片，所述第二晶片具有硅衬底，所述第二晶片的衬底具有设置在其上的硅 - 锗层，设置在所述硅 - 锗层上的硅层和设置在所述硅层上的氧化物层; 晶片接合第一和第二晶片; 以及从所述第二晶片去除所述衬底的不希望的部分以形成上硅层。 还公开了所得到的SOI晶片结构。

公开(公告)号：US06406986B1

公开(公告)日：2002-06-18

申请号：US09603046

申请日：2000-06-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L213205

CPC classification number: H01L29/66545 ,  H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4933

Abstract: A MOSFET has a drain region, a source region, and a channel region, and the MOSFET initially has a gate comprised of a capping layer on a polysilicon structure disposed on a gate dielectric over the channel region. A drain silicide and a source silicide having a first silicide thickness are formed in the drain region and the source region, respectively. A dielectric layer is deposited over the drain region, the source region, and the gate. The dielectric layer is polished until the capping layer of the gate is exposed such that the capping layer and the first dielectric layer are substantially level. The capping layer on the polysilicon structure of the gate is etched away such that the top of the polysilicon structure is exposed. A top portion of the first dielectric layer is etched away until sidewalls at a top portion of the polysilicon structure are exposed. A polysilicon spacer is formed at the exposed sidewalls at the top portion of the polysilicon structure. A silicidation metal is deposited on the top of the polysilicon structure that is exposed and on the polysilicon spacer. A silicidation anneal is performed with the silicidation metal and the polysilicon structure that is exposed and the polysilicon spacer to form a gate silicide having a second silicide thickness on top of the polysilicon structure of the gate. Because the gate silicide is formed with the added polysilicon spacer at the exposed sidewalls of the polysilicon structure, the gate silicide has a width that is larger than a width of the polysilicon structure of the gate. In addition, the gate silicide is formed in a separate step from the step for forming the drain silicide and the source silicide such that the gate silicide may have a larger thickness and be comprised of different metal silicide material from that of the drain silicide and the source silicide.

Abstract translation: MOSFET具有漏极区域，源极区域和沟道区域，并且MOSFET最初具有由在沟道区域上设置在栅极电介质上的多晶硅结构上的覆盖层构成的栅极。 在漏极区域和源极区域分别形成漏极硅化物和具有第一硅化物厚度的源硅化物。 在漏极区域，源极区域和栅极上沉积介电层。 电介质层被抛光直到栅极的覆盖层被暴露，使得覆盖层和第一介电层基本上是水平的。 栅极的多晶硅结构上的覆盖层被蚀刻掉，使得多晶硅结构的顶部被暴露。 第一介电层的顶部被蚀刻掉，直到多晶硅结构顶部的侧壁露出。 在多晶硅结构的顶部的暴露的侧壁处形成多晶硅间隔物。 在暴露的多晶硅结构的顶部和多晶硅间隔物上沉积硅化金属。 用硅化金属和暴露的多晶硅结构和多晶硅间隔物进行硅化退火，以在栅极的多晶硅结构的顶部形成具有第二硅化物厚度的栅极硅化物。 因为栅极硅化物在多晶硅结构的暴露的侧壁处由添加的多晶硅间隔物形成，所以栅极硅化物的宽度大于栅极的多晶硅结构的宽度。 此外，栅极硅化物在与用于形成漏极硅化物和源极硅化物的步骤分开的步骤中形成，使得栅极硅化物可以具有更大的厚度并且由漏极硅化物的不同的金属硅化物材料构成，并且 源硅化物。

公开(公告)号：US06403434B1

公开(公告)日：2002-06-11

申请号：US09779987

申请日：2001-02-09

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28194 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28525 ,  H01L29/517 ,  H01L29/7834

Abstract: A method of manufacturing an integrated circuit utilizes solid phase epitaxy to form an elevated source region and an elevated drain region. The method includes providing an amorphous semiconductor material and crystallizing the amorphous semiconductor material without damaging a high-k gate dielectric layer. The semiconductor material can be silicided. A shallow source drain implant can also be provide.

Abstract translation: 集成电路的制造方法利用固相外延形成升高的源极区域和升高的漏极区域。 该方法包括提供非晶半导体材料并使非晶半导体材料结晶而不损坏高k栅介质层。 半导体材料可以被硅化。 还可以提供浅源极漏极植入物。

公开(公告)号：US06399469B1

公开(公告)日：2002-06-04

申请号：US09613087

申请日：2000-07-10

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L213205

CPC classification number: H01L21/28123 ,  H01L21/2807 ,  H01L21/28114 ,  H01L29/49

Abstract: For fabricating a field effect transistor within an active device area of a semiconductor substrate, a first semiconductor layer of a first semiconductor material is deposited on a gate dielectric layer, and a second semiconductor layer of a second semiconductor material is deposited on the first semiconductor layer. A photoresist layer is deposited and patterned on the second semiconductor layer to form a gate photoresist structure on the second semiconductor layer. The gate photoresist structure is disposed over the active device area of the semiconductor substrate. Exposed regions of the second semiconductor layer, the first semiconductor layer, and the gate dielectric layer are etched continuously using a predetermined etch process to form a first gate structure from etching of the first semiconductor layer, a second gate structure from etching of the second semiconductor layer, and a gate dielectric from etching of the gate dielectric layer. A first etch rate of the first semiconductor material in the predetermined etch process is faster than in, a second etch rate of the second semiconductor material in the predetermined etch process such that a first length of the first gate structure and the gate electric is smaller than a second length of the second gate structure after the predetermined etch process. Thus, the first gate structure and the second gate structure form a notched gate structure of the field effect transistor for minimizing the overlap of the gate dielectric over the drain and source extensions of the field effect transistor to enhance the speed performance of the field effect transistor.

Abstract translation: 为了在半导体衬底的有源器件区域内制造场效应晶体管，在栅介质层上沉积第一半导体材料的第一半导体层，并且在第一半导体层上沉积第二半导体材料的第二半导体层 。 在第二半导体层上沉积并图案化光致抗蚀剂层，以在第二半导体层上形成栅极光致抗蚀剂结构。 栅极光致抗蚀剂结构设置在半导体衬底的有源器件区域上。 使用预定的蚀刻工艺连续地蚀刻第二半导体层，第一半导体层和栅极电介质层的暴露区域，以从第一半导体层的蚀刻形成第一栅极结构，从蚀刻第二半导体的第二栅极结构 层和栅极电介质，蚀刻栅极电介质层。 在预定蚀刻工艺中第一半导体材料的第一蚀刻速率比预定蚀刻工艺中的第二半导体材料的第二蚀刻速率快，使得第一栅极结构和栅极电的第一长度小于 在预定蚀刻工艺之后的第二栅极结构的第二长度。 因此，第一栅极结构和第二栅极结构形成场效应晶体管的缺口栅极结构，用于最小化场效应晶体管的漏极和源极延伸处的栅极电介质的重叠以增强场效应晶体管的速度性能 。

公开(公告)号：US06399427B1

公开(公告)日：2002-06-04

申请号：US09512092

申请日：2000-02-24

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2100

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/665 ,  H01L29/78621

Abstract: For forming a thin active device area on a SOI (semiconductor on insulator) substrate, an insulating structure is formed on the SOI (semiconductor on insulator) substrate. The insulating structure has an exposed surface. A second semiconductor substrate is pressed down onto the exposed surface of the insulating structure, and a downward and lateral force is applied on the second semiconductor substrate against the exposed surface of the insulating structure. The second semiconductor substrate is then removed away from the exposed surface of the insulating structure. The thin active device area is formed of a predetermined thickness of material of the second semiconductor substrate being deposited onto the exposed surface of the insulating structure from the second semiconductor substrate being pressed against the exposed surface of the insulating structure. The insulating structure is surrounded by a semiconductor material on the SOI substrate, and the predetermined thickness of material of the second semiconductor substrate is deposited onto the semiconductor material surrounding the insulating structure from the second semiconductor substrate being pressed against the exposed surface of the insulating structure. The present invention may be used to particular advantage when a field effect transistor is formed in the thin active device area with a drain extension, a source extension, and a channel region under a gate of the field effect transistor being formed in the thin active device area, and when a drain silicide and a source silicide of the field effect transistor is formed in the thicker semiconductor material surrounding the thin active device area.

Abstract translation: 为了在SOI（绝缘体上半导体）基板上形成薄的有源器件区域，在SOI（绝缘体上半导体）衬底上形成绝缘结构。 绝缘结构具有暴露的表面。 第二半导体衬底被压到绝缘结构的暴露表面上，并且向第二半导体衬底上施加向下和横向的力抵靠绝缘结构的暴露表面。 然后将第二半导体衬底从绝缘结构的暴露表面移开。 薄的有源器件区域由第二半导体衬底的预定厚度的材料形成，该第二半导体衬底的材料被沉积到绝缘结构的暴露表面上，该第二半导体衬底被压在绝缘结构的暴露表面上。 绝缘结构被SOI衬底上的半导体材料包围，并且将第二半导体衬底的材料的预定厚度沉积到围绕绝缘结构的半导体材料上，该第二半导体衬底被压在绝缘结构的暴露表面上 。 当在薄有源器件区域中形成场效应晶体管时，本发明可以被用于具有漏极延伸，源极延伸以及场效应晶体管的栅极下方的沟道区域形成在薄的有源器件中 并且当在较薄的有源器件区域周围的较厚的半导体材料中形成场效应晶体管的漏极硅化物和源极硅化物时。

公开(公告)号：US06391728B1

公开(公告)日：2002-05-21

申请号：US09804165

申请日：2001-03-12

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L29/6653

Abstract: The disclosure describes an exemplary embodiment relating to a method of forming halo regions in an integrated circuit. This method includes forming dummy spacer structures over an integrated circuit substrate proximate lateral side walls of a gate structure, providing an oxide layer over the integrated circuit substrate, removing the dummy spacer structures to create windows in the oxide layer exposing the integrated circuit substrate, providing an amorphization implant through the windows to form amorphous regions in the integrated circuit substrate, providing a halo dopant implant through the windows to the amorphous regions, and recrystallizating the amorphous regions in the integrated circuit substrate to form halo regions.

Abstract translation: 本公开描述了与在集成电路中形成晕圈的方法相关的示例性实施例。 该方法包括在栅极结构的横向侧壁附近在集成电路基板上形成虚拟间隔结构，在集成电路基板上提供氧化物层，去除虚设间隔结构以在暴露集成电路基板的氧化层中产生窗口，提供 通过窗户形成非晶化注入以在集成电路衬底中形成非晶区域，通过窗口向非晶区域提供晕轮掺杂剂注入，以及重结晶集成电路衬底中的非晶区域以形成晕圈。