公开(公告)号：US20030227787A1

公开(公告)日：2003-12-11

申请号：US10163848

申请日：2002-06-05

Applicant: STMicroelectronics Inc.

Inventor： Mark A. Lysinger ,  Christophe Frey ,  Frederic LaLanne

IPC: G11C015/00

CPC classification number: G11C15/04

Abstract: A Content Addressable Memory (CAM) cell is disclosed having an physical implementation of transistors for improving the semiconductor substrate area utilization of the CAM cell and the CAM array. The CAM cell comprises a first and second memory circuit and a compare circuit. The compare circuit of six transistors formed over two active regions. The local interconnect between the compare circuit and the first memory circuit formed of a polysilicon region. The local interconnect between the compare circuit and the second memory circuit formed of polysilicon and conductive regions.

Abstract translation: 公开了具有用于改善CAM单元和CAM阵列的半导体衬底区域利用率的晶体管的物理实现的内容寻址存储器（CAM）单元。 CAM单元包括第一和第二存储器电路和比较电路。 六个晶体管的比较电路形成在两个有源区域上。 比较电路和由多晶硅区域形成的第一存储器电路之间的局部互连。 比较电路和由多晶硅和导电区域形成的第二存储器电路之间的局部互连。

公开(公告)号：US20030220084A1

公开(公告)日：2003-11-27

申请号：US10154233

申请日：2002-05-22

Applicant: STMicroelectronics., Inc.

Inventor： Aleksej Makarov

IPC: H04B001/18

CPC classification number: H04L27/2332 ,  H04L27/2275 ,  H04L2027/0065 ,  H04L2027/0087

Abstract: Counter-clockwise and clockwise quadrant transitions are detected and accumulated with respect to a received complex signal over a certain time period. These transitions may then be compared in order to obtain information indicative of both a magnitude and phase of a frequency offset error. Additionally, zero-crossings of the received complex signal over the same certain time period are detected and accumulated. The accumulated crossings provide information indicative of frequency offset magnitude. The determined magnitude and phase of the frequency offset error may then be used to adjust a local oscillator frequency to provide for improved receiver performance.

Abstract translation: 在一段时间内相对于接收的复合信号检测并累积逆时针和顺时针象限转换。 然后可以比较这些转换，以获得指示频率偏移误差的幅度和相位的信息。 此外，检测并累积在相同的特定时间段内接收到的复信号的零交叉。 累积的交叉点提供指示频率偏移幅度的信息。 然后，频率偏移误差的确定幅度和相位可用于调整本地振荡器频率以提供改进的接收机性能。

公开(公告)号：US20030214318A1

公开(公告)日：2003-11-20

申请号：US10146407

申请日：2002-05-14

Applicant: STMicroelectronics, Inc.

Inventor： Thomas David Zounes

IPC: H03K019/00

CPC classification number: G01R31/318541 ,  G01R31/318572

Abstract: A method and apparatus for disabling the scan output of flip-flops contained within an integrated circuit. Registers within the integrated circuit form a serial shift register chain when in the test mode of operation. The registers contain therein flip-flops, each of the flip-flops having at least one data input, a scan test input, a data output, and a scan output. The flip-flop is capable of storing either the signal appearing on the at least one data input or the signal appearing on the scan test input, based on the mode of operation of the flip-flop The flip-flop includes a circuit coupled between the data output and the scan output for selectively disabling the scan output from following the value of the data output. Consequently, the scan output is enabled to output the logic value stored in the flip-flop when the flip-flop is in the test mode of operation and is disabled from outputting the logic value stored in the flip-flop when the flip-flop is in the normal mode of operation. When the scan output is disabled from following the data output, the scan output is driven to a predetermined logic value.

Abstract translation: 一种用于禁止包含在集成电路内的触发器的扫描输出的方法和装置。 在测试运行模式下，集成电路内的寄存器形成串行移位寄存器链。 寄存器中包含触发器，每个触发器具有至少一个数据输入，扫描测试输入，数据输出和扫描输出。 触发器能够基于触发器的操作模式存储出现在至少一个数据输入端上的信号或出现在扫描测试输入端的信号。触发器包括耦合在触发器 数据输出和扫描输出，用于选择性地禁用扫描输出跟随数据输出的值。 因此，当触发器处于测试操作模式时，扫描输出能够输出存储在触发器中的逻辑值，并且当触发器为0时禁止输出存储在触发器中的逻辑值 在正常工作模式下。 当扫描输出从数据输出之后被禁止时，扫描输出被驱动到预定的逻辑值。

公开(公告)号：US20030214021A1

公开(公告)日：2003-11-20

申请号：US10151656

申请日：2002-05-20

Applicant: STMICROELECTRONICS, INC.

Inventor： Tiao Zhou ,  Michael J. Hundt

IPC: H01L023/02

CPC classification number: H01L21/565 ,  H01L23/3121 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit die having an active area that must remain exposed after packaging is secured by a compliant die attachment by which the integrated circuit die is held in position within a transfer mold during encapsulation. The compliant die attachment may comprise a flexible, compressible tape having pressure-sensitive adhesive, alone or with a rigid substrate support, or a compliant adhesive preferably applied only around a periphery of the die attach area. Deformation of the compliant die attachment under mold clamping pressure allows complete contact of the mold with the active area, preventing bleeding of the encapsulating material under the edge of a mold portion onto the active area.

Abstract translation: 具有必须在包装后必须保持暴露的有源区域的集成电路管芯通过柔性管芯附件来固定，通过该柔性管芯附件，集成电路管芯在封装期间保持在转移模具内就位。 柔性芯片附件可以包括具有压敏粘合剂的柔性可压缩带，其单独地或具有刚性基板支撑件，或者柔性粘合剂优选仅在芯片附着区域的周围施加。 在模具夹紧压力下，柔性模具附件的变形允许模具与活动区域完全接触，防止模具部件边缘下方的封装材料渗透到活动区域上。

公开(公告)号：US20030210687A1

公开(公告)日：2003-11-13

申请号：US10141560

申请日：2002-05-08

Applicant: STMicroelectronics, Inc.

Inventor： Ge Nong

IPC: H04L012/28 ,  H04L012/56

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/3081 ,  H04L2012/5652 ,  H04L2012/5681

Abstract: A packet switch capable of receiving fixed size data cells from N input ports and transmitting the fixed size data cells to N output ports. The packet switch comprises: 1) a frame deserializer for receiving the data cells as serial bits from the N input ports and transmitting the data cells as parallel bits in data frames containing a plurality of data cells, wherein each of the plurality of data cells in each data frame are destined for a common output port; 2) a frame serializer for receiving the data frames and transmitting the plurality of data cells in the data frames as serial bits to the N output ports; and 3) a shared buffer coupling the frame deserializer and the frame serializer for receiving and buffering the data frames from the frame deserializer and transmitting the buffered data frames to the frame serializer.

Abstract translation: 一种分组交换机，能够从N个输入端口接收固定大小的数据信元，并将固定大小的数据信元发送到N个输出端口。 分组交换机包括：1）帧解串器，用于从N个输入端口接收作为串行比特的数据单元，并将数据单元作为包含多个数据单元的数据帧中的并行比特发送，其中多个数据单元中的每一个在 每个数据帧都注定为公共输出端口; 2）一种帧序列化器，用于接收数据帧并将数据帧中的多个数据信元作为串行位发送到N个输出端口; 以及3）耦合帧解串器和帧串行器的共享缓冲器，用于从帧解串器接收和缓冲数据帧，并将缓冲的数据帧发送到帧序列化器。

公开(公告)号：US20030198378A1

公开(公告)日：2003-10-23

申请号：US10125028

申请日：2002-04-18

Applicant: STMICROELECTRONICS, INC.

Inventor： Kim Chai Ng

IPC: G06K009/00

CPC classification number: G06K9/20 ,  G06K2209/40 ,  G06T7/55

Abstract: An image processing system and method for smoothing irregularities from 3D image information that was reconstructed from a plurality of 2D views of a scene, and particularly from homogeneous surfaces of objects in a scene. The method defines a window that overlaps a plurality of pixels of one of a plurality of 2D image views of a scene. Each pixel is associated with predefined 3D depth information, and further is associated with a matching curve. A subject pixel is located within the plurality of pixels overlapped by the window. The method calculates an average 3D depth information associated with the plurality of pixels overlapped by the window, and assigns the calculated average 3D depth information to the 3D depth information of the subject pixel, if the calculated average 3D depth information is within an error region of a matching curve associated with the subject pixel.

Abstract translation: 一种用于从3D场景的多个2D视图重建的3D图像信息中平滑不规则的图像处理系统和方法，特别是从场景中的物体的均匀表面。 该方法定义了与场景的多个2D图像视图中的一个的多个像素重叠的窗口。 每个像素与预定义的3D深度信息相关联，并且还与匹配曲线相关联。 被摄体像素位于由窗口重叠的多个像素内。 该方法计算与由窗口重叠的多个像素相关联的平均3D深度信息，并且如果所计算的平均3D深度信息在所述目标像素的误差区域内，则将计算出的平均3D深度信息分配给对象像素的3D深度信息 与对象像素相关联的匹配曲线。

公开(公告)号：US20030146507A1

公开(公告)日：2003-08-07

申请号：US10061507

申请日：2002-02-01

Applicant: STMicroelectronics, Inc.

Inventor： Tiao Zhou ,  Michael J. Hundt

IPC: H01L023/52

CPC classification number: H01L24/49 ,  H01L23/36 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A thermally-enhanced ball grid array package structure is provided that includes an integrated circuit chip, a heat spreader and a substrate. The integrated circuit chip has a specified surface area. The heat spreader is coupled to the integrated circuit chip. The substrate is coupled to the heat spreader. The substrate has a specified surface area. The heat spreader covers a specified portion of the surface area of the substrate that is greater than the surface area of the integrated circuit chip. The heat spreader is operable to dissipate heat from the integrated circuit chip over the specified portion of the surface area of the substrate.

Abstract translation: 提供了一种热增强球栅阵列封装结构，其包括集成电路芯片，散热器和基板。 集成电路芯片具有指定的表面积。 散热器耦合到集成电路芯片。 衬底耦合到散热器。 基板具有指定的表面积。 散热器覆盖大于集成电路芯片的表面积的基板的表面积的指定部分。 散热器可操作以从集成电路芯片散热超过衬底表面区域的指定部分。

公开(公告)号：US20030141595A1

公开(公告)日：2003-07-31

申请号：US10066422

申请日：2002-01-31

Applicant: STMicroelectronics, Inc.

Inventor： Anthony M. Chiu ,  Harry Michael Siegel

IPC: H01L023/48

CPC classification number: H01L21/481 ,  H01L21/4857 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/09781 ,  H05K2201/09881 ,  H05K2203/0278 ,  H01L2924/00014

Abstract: A system and method is disclosed for providing mechanical planarization of a sequential build up substrate for an integrated circuit package. A planarization plate is placed in contact with an uneven external surface of a dielectric layer that covers underlying functional circuit elements and filler circuit elements. A heating element in the planarization plate flattens protruding portions of the external surface of the dielectric layer to create a flat external surface on the dielectric layer. After the flat external surface of the dielectric layer has cooled, it is then covered with a metal conductor layer. The method of the present invention increases the number of sequential buildup layers that may be placed on a sequential buildup substrate.

Abstract translation: 公开了一种用于为集成电路封装提供顺序建立衬底的机械平面化的系统和方法。 平面化板被放置成与覆盖下面的功能电路元件和填充电路元件的电介质层的不平坦外表面接触。 平面化板中的加热元件使电介质层的外表面的突出部分变平，以在电介质层上形成平坦的外表面。 在电介质层的平坦外表面冷却之后，用金属导体层覆盖。 本发明的方法增加了可以放置在顺序生成基板上的连续堆积层的数量。

公开(公告)号：US20030123454A1

公开(公告)日：2003-07-03

申请号：US10290766

申请日：2002-11-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Faraydon O. Karim ,  Ramesh Chandra ,  Bernd H. Stramm

IPC: H04L012/28

CPC classification number: H04L49/9031 ,  H04L49/90 ,  H04L49/901

Abstract: A circular buffer storing packets for processing by one or more network processors employs an empty buffer address register identifying where a next received packet should be stored, a next packet address register identifying the next packet to be processed, and a packet-processing address register within each network processor identifying the packet being processed by that network processor. The n-bit addresses to the buffer are mapped or masked from/to the m-bit packet-processing address registers by software, allowing the buffer size to be fully scalable. A dedicated packet retrieval instruction supported by the network processor(s) retrieves a new packet for processing using the next packet address register and copies that into the associated packet-processing address register for use in subsequent accesses. Buffer management is thus independent of the network processor architecture.

Abstract translation: 存储用于由一个或多个网络处理器处理的分组的循环缓冲器使用空缓冲器地址寄存器来标识下一个接收到的分组应该被存储在哪里，下一个分组地址寄存器标识下一个待处理分组，以及一个分组处理地址寄存器 每个网络处理器识别由该网络处理器正在处理的分组。 缓冲区的n位地址通过软件从/到m位数据包处理地址寄存器映射或屏蔽，从而允许缓冲区大小完全可扩展。 由网络处理器支持的专用分组检索指令使用下一个分组地址寄存器检索新的分组进行处理，并将其复制到相关的分组处理地址寄存器中以用于随后的访问。 因此，缓冲区管理与网络处理器架构无关。

公开(公告)号：US20030117963A1

公开(公告)日：2003-06-26

申请号：US10028805

申请日：2001-12-19

Applicant: STMicroelectronics, Inc.

Inventor： Xianbin Wang

IPC: H04L001/00 ,  H04J003/16

CPC classification number: H04L5/143 ,  H04L5/023

Abstract: To improve the performance of DSL modems, a DSL duplexing ratio for a new communication is selected according to the communications needs of an application. A required upstream and downstream bit rate for application communications is determined. From the ratio of these bit rates, a desired duplexing ratio is calculated. The operation of the modem is then adapted to choose a duplexing ratio that approximates the desired duplexing ratio for the application. To optimize modem operation, the size and position of the upstream and downstream bandwidths used for transmission are intelligently selected when the bit rate necessary for making the transmission is less than the total available bandwidth provided by the chosen duplexing ratio. By intelligently selecting a minimum number of subcarriers for Digital Multi-tone (DMT) signal transmission, a reduction in line driver power consumption is effectuated. Additionally, by intelligently selecting the position of the used bandwidth within the total available bandwidth, near-end crosstalk (NEXT) noise may be minimized.

Abstract translation: 为了提高DSL调制解调器的性能，根据应用的通信需要选择新通信的DSL双工比。 确定应用通信所需的上行和下行比特率。 根据这些比特率的比率，计算期望的双工比。 调制解调器的操作然后适于选择近似于应用的期望双工比的双工比率。 为了优化调制解调器操作，当用于进行传输所需的比特率小于由选择的双工比提供的总可用带宽时，用于传输的上行和下行带宽的大小和位置被智能地选择。 通过智能地选择用于数字多音（DMT）信号传输的最小数量的子载波，实现了线路驱动器功耗的降低。 此外，通过智能地选择所使用的带宽在总可用带宽内的位置，近端串扰（NEXT）噪声可能被最小化。