公开(公告)号：US12041730B2

公开(公告)日：2024-07-16

申请号：US17446741

申请日：2021-09-02

Applicant: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： Seok Kim Tay ,  Mikael Tuominen ,  Kim Liu

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H05K1/18

CPC classification number: H05K3/4655 ,  H01L21/4857 ,  H01L23/49822 ,  H05K1/185 ,  H05K2203/111

Abstract: A method of manufacturing a component carrier is described. The method includes forming a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure, and reducing an amount of solvent in a fiber-free dielectric layer, which is directly connected to a metal layer, so that the dielectric layer with reduced amount of solvent remains at least partially uncured.

公开(公告)号：US11956904B2

公开(公告)日：2024-04-09

申请号：US16952021

申请日：2020-11-18

Applicant: STEMCO CO., LTD.

Inventor： Jae Soo Lee ,  Hyo Jin Park ,  Sung Jin Lee ,  Dong Gon Kim

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K3/4602 ,  H05K1/0298 ,  H05K3/4655 ,  H05K2201/0959 ,  H05K2203/13

Abstract: The present invention provides a multilayer circuit board and a method for manufacturing the same for improving a bowing problem that occurs when manufacturing the multilayer circuit board. A multilayer circuit board according to the present invention is a board having a patterned layer that functions as a circuit a base layer, and includes: a second pattern layer formed on one side of the base layer; a first pattern layer formed on the second pattern layer; and an interlayer insulating layer formed between the first pattern layer and the second pattern layer, the interlayer insulating layer being partially formed on the second pattern layer so as to correspond to a region where the first pattern layer is formed.

公开(公告)号：US11937377B2

公开(公告)日：2024-03-19

申请号：US17503360

申请日：2021-10-18

Applicant: SHENNAN CIRCUITS CO., LTD.

Inventor： Changsheng Tang

IPC: H05K3/00 ,  H01L21/768 ,  H01L23/522 ,  H05K1/11 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/0035 ,  H01L21/76802 ,  H01L21/76832 ,  H01L23/5226 ,  H05K1/115 ,  H05K3/0038 ,  H05K3/4069 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09827

Abstract: The main technical problem solved by the present disclosure is to provide a circuit board preparation method. The method includes: obtaining a to-be-processed plate comprising an insulating layer, a first copper layer, a second copper layer opposite to the first copper layer, a blind metalized hole, and a first tab facing the blind metalized hole; obtaining a white insulating material; laminating the white insulating material to a surface of the insulating layer, a surface of the first copper layer, a surface of the first tab, and a surface of the second copper layer to form a first white insulating medium layer and a second white insulating medium layer opposite to the first while insulating medium layer; and performing surface polishing for the first white insulating medium layer and grinding the first white insulating medium layer until the first tab is exposed to form a first white reflective layer.

公开(公告)号：US11700685B2

公开(公告)日：2023-07-11

申请号：US17512901

申请日：2021-10-28

Applicant: Avary Holding (Shenzhen) Co., Limited. ,  QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD

Inventor： Fu-Yun Shen ,  Xian-Qin Hu

IPC: H05K1/09 ,  H05K3/06 ,  H01L23/13 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/024 ,  H05K1/0219 ,  H05K3/4602 ,  H05K3/4655 ,  H05K2201/0723 ,  H05K2201/09063

Abstract: A circuit board with reduced dielectric losses enabling the movement of high frequency signals includes an inner circuit board and two outer circuit boards. The inner circuit board includes a first conductor layer and a first substrate layer. The first conductor layer includes a signal line and two ground lines on both sides of the signal line. The first substrate layer covers a side of the first conductor layer and defines first through holes which expose the signal line. Each outer circuit board includes a second substrate layer and a second conductor layer. The second substrate layer abuts the inner circuit board and defines second through holes which are not aligned with the first through holes, partially surrounding the signal line with air which has a very low dielectric constant. A method for manufacturing the high-frequency circuit board is also disclosed.

公开(公告)号：US20190215959A1

公开(公告)日：2019-07-11

申请号：US16245396

申请日：2019-01-11

Applicant: IBIDEN CO., LTD.

Inventor： Takema ADACHI ,  Toshihide MAKINO ,  Hidetoshi NOGUCHI

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/40

CPC classification number: H05K1/116 ,  H05K1/113 ,  H05K3/4015 ,  H05K3/4655 ,  H05K3/4688

Abstract: A printed wiring board includes a core substrate, a first build-up layer, and a second build-up layer. The core substrate includes a core layer, through-hole conductors and through-hole lands. Metal foils of the through-hole lands in the core substrate have mat surfaces at interfaces of the core layer in the core substrate, metal foils of via lands in the build-up layers have inner mat surfaces at interfaces of insulating layers, and metal foils of outermost conductor layers in the build-up layers have outermost mat surfaces at interfaces of outermost insulating layers. Ten-point average roughness (RzI1) of the inner first mat surface is smaller than each of ten-point average roughness (Rz1, Rz2) of the mat surfaces and ten-point average roughness (RzO1, RzO2) of the outermost mat surfaces. Ten-point average roughness (RzI2) of the inner second mat surface is smaller than each of the ten-point average roughness (Rz1, Rz2, RzO1, RzO2).

公开(公告)号：US20180324960A1

公开(公告)日：2018-11-08

申请号：US15967955

申请日：2018-05-01

Applicant: Skyworks Solutions, Inc.

Inventor： Ki Wook Lee

IPC: H05K3/46

CPC classification number: H05K3/4697 ,  H01Q1/38 ,  H01Q9/0407 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/005 ,  H05K3/06 ,  H05K3/4038 ,  H05K3/4623 ,  H05K3/4655

Abstract: A method of making a printed circuit board structure including a closed cavity is provided. The method can include the steps of forming a cavity in a core structure of a core layer, laminating each of a top surface and a bottom surface of the core structure with an adhesive layer and a metal layer to prepare a laminate structure and cover the cavity to define a closed cavity. The method also includes forming vias through the laminate structure, and patterning the metal layers in the laminate structure.

公开(公告)号：US20180255666A1

公开(公告)日：2018-09-06

申请号：US15912067

申请日：2018-03-05

Applicant: Laird Technologies, Inc.

Inventor： Jason L. STRADER ,  Eugene Anthony PRUSS ,  Gerald R. ENGLISH

IPC: H05K9/00 ,  B32B37/20 ,  H05K1/03 ,  H05K3/32 ,  H05K3/46

CPC classification number: H05K9/0024 ,  B26F1/00 ,  B32B37/206 ,  B32B38/04 ,  B32B2309/02 ,  B32B2309/12 ,  B32B2457/08 ,  H05K1/0216 ,  H05K1/0393 ,  H05K3/321 ,  H05K3/4655 ,  H05K3/4658 ,  H05K3/4691 ,  H05K9/003 ,  H05K9/0084 ,  H05K2201/0195 ,  H05K2201/0715 ,  H05K2201/10371

Abstract: According to various aspects, disclosed are exemplary embodiments of a multilayered thin film board level shield and exemplary embodiments of a system in package that comprise a a multilayer flexible board level shield. Also disclosed are exemplary embodiments of methods relating to making multilayer thin film board level shields. Additional exemplary embodiments are disclosed of systems and methods of applying board level shielding.

公开(公告)号：US09232636B2

公开(公告)日：2016-01-05

申请号：US13992189

申请日：2011-02-18

Applicant: Takayoshi Ozeki ,  Yohsuke Ishikawa ,  Yoshiaki Esaki ,  Hiroyuki Fukusumi

Inventor： Takayoshi Ozeki ,  Yohsuke Ishikawa ,  Yoshiaki Esaki ,  Hiroyuki Fukusumi

IPC: B32B3/00 ,  H05K1/02 ,  C08G69/48 ,  C08L77/00 ,  H05K1/03 ,  H05K3/46 ,  C08G59/54 ,  C08G59/62 ,  C08L63/00

CPC classification number: H05K1/0281 ,  C08G59/54 ,  C08G59/623 ,  C08G69/48 ,  C08L63/00 ,  C08L77/00 ,  H05K1/0298 ,  H05K1/0326 ,  H05K1/0346 ,  H05K1/0393 ,  H05K3/4655 ,  H05K2201/0195

Abstract: The flexible printed wiring board according to the present invention includes a first flexible insulating layer, a first conductor wiring laminated on the first insulating layer, a second single-layered insulating layer laminated on the first insulating layer, as it covers the first conductor wiring, and a second conductor wiring laminated on the second insulating layer. The first conductor wiring has a thickness in the range of 10 to 30 μm, a line width in the range of 50 μm to 1 mm, and a line gap in the range of 50 μm to 1 mm. The thickness from the surface of the first conductor wiring to the surface of the second insulating layer is in the range of 5 to 30 μm. The surface waviness of the part of the second insulating layer covering the first conductor wiring is 10 μm or less.

Abstract translation: 根据本发明的柔性印刷电路板包括第一柔性绝缘层，层叠在第一绝缘层上的第一导体布线，层叠在第一绝缘层上的第二单层绝缘层，因为它覆盖第一导体布线， 以及层压在所述第二绝缘层上的第二导体布线。 第一导体布线的厚度为10〜30μm，线宽为50μm〜1mm，线间隔为50μm〜1mm的范围。 从第一导体布线的表面到第二绝缘层的表面的厚度在5〜30μm的范围内。 覆盖第一导体布线的第二绝缘层的部分的表面波纹为10μm以下。

公开(公告)号：US20150305154A1

公开(公告)日：2015-10-22

申请号：US14417592

申请日：2013-07-25

Applicant: KYOCERA Corporation

Inventor： Katsura HAYASHI ,  Keisaku MATSUMOTO

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K1/112 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/15174 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/4602 ,  H05K3/4655 ,  H05K2201/0175 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/029

Abstract: A wiring board includes a first electrically-conductive layer; and a first resin layer covering the first electrically-conductive layer, the first resin layer including a resin portion and inorganic insulating particles dispersed in the resin portion. The first resin layer has a first layer region which is in contact with one main surface and side surfaces of the first electrically-conductive layer, and a second layer region which is located on a side of the first layer region which side is opposite to the first electrically-conductive layer. The inorganic insulating particles include a plurality of first inorganic insulating particles contained in the first layer region, and a plurality of second inorganic insulating particles contained in the second layer region. A content rate of the first inorganic insulating particles in the first layer region is lower than a content rate of the second inorganic insulating particles in the second layer region.

Abstract translation: 布线基板包括第一导电层; 以及覆盖第一导电层的第一树脂层，第一树脂层包括树脂部分和分散在树脂部分中的无机绝缘颗粒。 所述第一树脂层具有与所述第一导电层的一个主面和侧面接触的第一层区域和位于所述第一层区域的与所述第一导电层相反的一侧的第二层区域 第一导电层。 无机绝缘粒子包括在第一层区域中包含的多个第一无机绝缘粒子和包含在第二层区域中的多个第二无机绝缘粒子。 第一层区域中的第一无机绝缘粒子的含有率低于第二层区域中的第二无机绝缘粒子的含有率。

公开(公告)号：US20150068788A1

公开(公告)日：2015-03-12

申请号：US14485069

申请日：2014-09-12

Applicant: IBIDEN Co., Ltd.

Inventor： Tetsuo AMANO ,  Toshio Nishiwaki

IPC: H05K1/03 ,  H05K1/09 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0306 ,  H05K1/0219 ,  H05K1/024 ,  H05K1/0271 ,  H05K1/0373 ,  H05K1/09 ,  H05K1/115 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4655 ,  H05K2201/0145 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/096

Abstract: A printed wiring board includes a core insulation layer including a resin and having a via conductor through the core insulation layer, a first conductive layer formed on the core layer and including a copper foil and a plated film, an interlayer insulation layer formed on the first layer and including a resin, the interlayer layer having a via conductor through the interlayer layer, and a second conductive layer formed on the interlayer layer and including a copper foil and a plated film. The first layer includes a conductive circuit, the core and interlayer layers have dielectric constants of 4.0 or lower for signal transmission at frequency of 1 GHz and thermal expansion coefficient of 85 ppm/° C. or lower at or below Tg, and the foil of the first layer has thickness greater than thickness of the foil of the second layer.

Abstract translation: 印刷布线板包括：芯绝缘层，其包括树脂，并且具有通过芯绝缘层的通路导体，形成在芯层上并包括铜箔和镀膜的第一导电层，形成在第一层上的层间绝缘层 层，并且包括树脂，所述层间层具有穿过所述层间层的通孔导体，以及形成在所述中间层上并包括铜箔和镀膜的第二导电层。 第一层包括导电电路，核心层和层间介电常数为4.0或更低，信号传输频率为1GHz，热膨胀系数为85ppm /℃或更低，等于或低于Tg， 第一层的厚度大于第二层的箔的厚度。