公开(公告)号：US20030141595A1

公开(公告)日：2003-07-31

申请号：US10066422

申请日：2002-01-31

Applicant: STMicroelectronics, Inc.

Inventor： Anthony M. Chiu ,  Harry Michael Siegel

IPC: H01L023/48

CPC classification number: H01L21/481 ,  H01L21/4857 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/09781 ,  H05K2201/09881 ,  H05K2203/0278 ,  H01L2924/00014

Abstract: A system and method is disclosed for providing mechanical planarization of a sequential build up substrate for an integrated circuit package. A planarization plate is placed in contact with an uneven external surface of a dielectric layer that covers underlying functional circuit elements and filler circuit elements. A heating element in the planarization plate flattens protruding portions of the external surface of the dielectric layer to create a flat external surface on the dielectric layer. After the flat external surface of the dielectric layer has cooled, it is then covered with a metal conductor layer. The method of the present invention increases the number of sequential buildup layers that may be placed on a sequential buildup substrate.

Abstract translation: 公开了一种用于为集成电路封装提供顺序建立衬底的机械平面化的系统和方法。 平面化板被放置成与覆盖下面的功能电路元件和填充电路元件的电介质层的不平坦外表面接触。 平面化板中的加热元件使电介质层的外表面的突出部分变平，以在电介质层上形成平坦的外表面。 在电介质层的平坦外表面冷却之后，用金属导体层覆盖。 本发明的方法增加了可以放置在顺序生成基板上的连续堆积层的数量。

公开(公告)号：US20030193072A1

公开(公告)日：2003-10-16

申请号：US10123685

申请日：2002-04-16

Applicant: STMICROELECTRONICS, INC.

Inventor： Anthony M. Chiu ,  Harry Michael Siegel

IPC: H01L027/14 ,  H01L029/82 ,  H01L029/84

CPC classification number: G06K9/0002

Abstract: A flat filter layer is received between upper and lower mold portions of a mold for packaging an integrated circuit sensor device, held by the mold over and in contact with the integrated circuit's sensing surface, in light compression between the sensing surface and a mold surface. The filter layer includes slots allowing passage of injected encapsulating material to cover the integrated circuit die, with overlap portions embedded in the encapsulating material, while preventing such encapsulating material from flowing onto the sensing surface. The filter layer may be, for example, a liquid and/or light filter, and may include a protective or supportive backing. The filter is thus affixed to the packaged integrated circuit sensor device, while mold residue is reduced and mold life extended.

Abstract translation: 在模具的上模具部分和下模具部分之间容纳平坦的过滤层，用于将由模具保持的集成电路传感器装置封装在集成电路的感测表面上并与集成电路的感测表面接触，以在感测表面和模具表面之间的轻压缩。 过滤层包括允许注入的封装材料通过以覆盖集成电路管芯的槽，其中重叠部分嵌入在封装材料中，同时防止这种封装材料流入感测表面。 过滤层可以是例如液体和/或光过滤器，并且可以包括保护性或支撑性背衬。 因此，过滤器被固定到封装的集成电路传感器装置上，同时减少模具残渣并延长模具寿命。

公开(公告)号：US20030167632A1

公开(公告)日：2003-09-11

申请号：US10091743

申请日：2002-03-06

Applicant: STMicroelectronics, Inc.

Inventor： Danielle A. Thomas ,  Harry Michael Siegel ,  Antonio A. Do Bento Vieira ,  Anthony M. Chiu

IPC: H05K003/30 ,  H05K003/34

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49155 ,  H01L2924/00014

Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.

Abstract translation: 公开了用于在集成电路中提供再分配金属层的系统和方法。 在施加最终钝化之前，在集成电路的制造期间，由分布金属层由集成电路中的最后一个金属层形成。 最后一个金属层提供了用于倒装芯片互连的焊料凸块的位置。 再分布金属层可以是（1）通过介电层中的开口沉积在下一个最后金属层上的平坦层，或（2）沉积在连接到最后一个金属层上的通孔阵列上。 焊锡凸块之间的空间沉积有较窄的走线，用于连接下面的有源电路区域。 沉积最后的钝化层以确保产品的可靠性。

公开(公告)号：US20030143406A1

公开(公告)日：2003-07-31

申请号：US10066245

申请日：2002-01-31

Applicant: STMicroelectronics, Inc.

Inventor： Harry Michael Siegel ,  Anthony M. Chiu

IPC: B32B009/04 ,  B29C045/00

CPC classification number: H01L21/566 ,  H01L23/3107 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

Abstract: A system and method is disclosed for using a pre-formed film in a transfer molding process of the type that uses a transfer mold to encapsulate portions of an integrated circuit with a molding compound. A film of compliant material is pre-formed to conform the shape of the film to a mold cavity surface of the transfer mold. The pre-formed film is then placed adjacent to the surfaces of the mold cavity of the transfer mold. The mold cavity is filled with molding compound and the integrated circuit is encapsulated. The pre-formation of the film allows materials to be used that are not suitable for use with prior art methods.

Abstract translation: 公开了一种用于在传递模塑工艺中使用预成型膜的系统和方法，该方法使用转移模具将模制化合物的集成电路的部分封装。 预先形成柔顺材料薄膜以使膜的形状符合转移模具的模腔表面。 然后将预成型的膜放置在传送模具的模腔的表面附近。 模腔充满模塑料，集成电路封装。 该膜的预成型允许使用不适用于现有技术方法的材料。

公开(公告)号：US20030140678A1

公开(公告)日：2003-07-31

申请号：US10062595

申请日：2002-01-31

Applicant: STMicroelectronics, Inc.

Inventor： Harry Michael Siegel ,  Anthony M. Chiu

IPC: B21J013/04

CPC classification number: H01L21/52 ,  H01L23/544 ,  H01L24/48 ,  H01L24/83 ,  H01L2223/54473 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/854 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A system and method is disclosed for aligning an integrated circuit die on an integrated circuit substrate. A plurality of deposits of deformable material are placed on the substrate where the integrated circuit die is to be aligned. In one advantageous embodiment a stamping tool is indexed to a first tooling hole and to a second tooling hole in the substrate. The stamping tool imprints the deposits of deformable material to a tolerance of less than one hundred microns with respect to the first and second tooling holes. The imprinted portions of the deposits to form a pocket for receiving the integrated circuit die. This enables the integrated circuit die to be precisely aligned on the substrate in three dimensions.

Abstract translation: 公开了用于使集成电路基板上的集成电路管芯对准的系统和方法。 将多个可变形材料的沉积物放置在集成电路芯片对准的基板上。 在一个有利的实施例中，冲压工具被转位到第一工具孔和衬底中的第二工具孔。 冲压工具将可变形材料的沉积物相对于第一和第二工具孔印刷到小于百微米的公差。 沉积物的印迹部分形成用于接收集成电路管芯的口袋。 这使得集成电路管芯能够在三维尺寸上精确地对准衬底。

公开(公告)号：US20040017661A1

公开(公告)日：2004-01-29

申请号：US10205715

申请日：2002-07-26

Applicant: STMicroelectronics, Inc.

Inventor： Harry Michael Siegel

IPC: H05K007/20

CPC classification number: H01L23/36 ,  H01L23/3121 ,  H01L23/4006 ,  H01L23/4093 ,  H01L2023/4043 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2924/1815

Abstract: A method for removing heat from an active area of an integrated circuit device is provided. The method includes applying a separator to the active area of the integrated circuit device. A thermally conductive element is coupled to the active area of the integrated circuit device outwardly of the separator.

Abstract translation: 提供了一种从集成电路器件的有源区域除去热量的方法。 该方法包括将分离器应用于集成电路器件的有源区。 导热元件在分离器外部耦合到集成电路装置的有源区域。

公开(公告)号：US20040017000A1

公开(公告)日：2004-01-29

申请号：US10400207

申请日：2003-03-27

Applicant: STMicroelectronics, Inc.

Inventor： Anthony M. Chiu ,  Harry Michael Siegel

IPC: H01L023/02

CPC classification number: H01L24/48 ,  G06K9/0002 ,  H01L21/565 ,  H01L23/3107 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4848 ,  H01L2224/85051 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: An integrated circuit (IC) device comprising: 1) an integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and sidewalls extending between the first surface and the second surface; 2) an integrated circuit (IC) package for supporting the IC die, wherein the IC package is attached to at least one of the sidewalls of the IC die such that at least a portion of the IC die first surface and at least a portion of the IC die second surface are exposed; and 3) at least one auxiliary component attached to at least one of the exposed portion of the IC die first surface and the exposed portion of the IC die second surface.

Abstract translation: 1.一种集成电路（IC）装置，包括：1）具有第一表面，与第一表面相对的第二表面和在第一表面和第二表面之间延伸的侧壁的集成电路（IC）模具; 2）一种用于支持IC芯片的集成电路（IC）封装，其中IC封装被附接到IC芯片的至少一个侧壁，使得IC的至少一部分裸片的第一表面和至少一部分 IC芯片第二表面露出; 以及3）至少一个辅助部件，其附接到IC管芯第一表面的暴露部分和IC裸片第二表面的暴露部分中的至少一个。