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    Embedded flat film molding
    1.
    发明申请
    Embedded flat film molding 有权
    嵌入式平膜成型

    公开(公告)号：US20030193072A1

    公开(公告)日：2003-10-16

    申请号：US10123685

    申请日：2002-04-16

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Anthony M. Chiu ,  Harry Michael Siegel

    IPC: H01L027/14 ,  H01L029/82 ,  H01L029/84

    CPC classification number: G06K9/0002

    Abstract: A flat filter layer is received between upper and lower mold portions of a mold for packaging an integrated circuit sensor device, held by the mold over and in contact with the integrated circuit's sensing surface, in light compression between the sensing surface and a mold surface. The filter layer includes slots allowing passage of injected encapsulating material to cover the integrated circuit die, with overlap portions embedded in the encapsulating material, while preventing such encapsulating material from flowing onto the sensing surface. The filter layer may be, for example, a liquid and/or light filter, and may include a protective or supportive backing. The filter is thus affixed to the packaged integrated circuit sensor device, while mold residue is reduced and mold life extended.

    Abstract translation: 在模具的上模具部分和下模具部分之间容纳平坦的过滤层，用于将由模具保持的集成电路传感器装置封装在集成电路的感测表面上并与集成电路的感测表面接触，以在感测表面和模具表面之间的轻压缩。 过滤层包括允许注入的封装材料通过以覆盖集成电路管芯的槽，其中重叠部分嵌入在封装材料中，同时防止这种封装材料流入感测表面。 过滤层可以是例如液体和/或光过滤器，并且可以包括保护性或支撑性背衬。 因此，过滤器被固定到封装的集成电路传感器装置上，同时减少模具残渣并延长模具寿命。

    SYSTEM AND METHOD FOR PROVIDING MECHANICAL PLANARIZATION OF A SEQUENTIAL BUILD UP SUBSTRATE FOR AN INTEGRATED CIRCUIT PACKAGE
    5.
    发明申请
    SYSTEM AND METHOD FOR PROVIDING MECHANICAL PLANARIZATION OF A SEQUENTIAL BUILD UP SUBSTRATE FOR AN INTEGRATED CIRCUIT PACKAGE 有权
    用于提供用于集成电路封装的顺序建立基板的机械平面化的系统和方法

    公开(公告)号：US20030141595A1

    公开(公告)日：2003-07-31

    申请号：US10066422

    申请日：2002-01-31

    Applicant: STMicroelectronics, Inc.

    Inventor： Anthony M. Chiu ,  Harry Michael Siegel

    IPC: H01L023/48

    CPC classification number: H01L21/481 ,  H01L21/4857 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/09781 ,  H05K2201/09881 ,  H05K2203/0278 ,  H01L2924/00014

    Abstract: A system and method is disclosed for providing mechanical planarization of a sequential build up substrate for an integrated circuit package. A planarization plate is placed in contact with an uneven external surface of a dielectric layer that covers underlying functional circuit elements and filler circuit elements. A heating element in the planarization plate flattens protruding portions of the external surface of the dielectric layer to create a flat external surface on the dielectric layer. After the flat external surface of the dielectric layer has cooled, it is then covered with a metal conductor layer. The method of the present invention increases the number of sequential buildup layers that may be placed on a sequential buildup substrate.

    Abstract translation: 公开了一种用于为集成电路封装提供顺序建立衬底的机械平面化的系统和方法。 平面化板被放置成与覆盖下面的功能电路元件和填充电路元件的电介质层的不平坦外表面接触。 平面化板中的加热元件使电介质层的外表面的突出部分变平，以在电介质层上形成平坦的外表面。 在电介质层的平坦外表面冷却之后，用金属导体层覆盖。 本发明的方法增加了可以放置在顺序生成基板上的连续堆积层的数量。

    Method of eliminating uncontrolled voids in sheet adhesive layer
    8.
    发明申请
    Method of eliminating uncontrolled voids in sheet adhesive layer 有权
    消除薄片粘合剂层中不受控制的空隙的方法

    公开(公告)号：US20020149106A1

    公开(公告)日：2002-10-17

    申请号：US09835306

    申请日：2001-04-13

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Anthony M. Chiu

    IPC: H01L023/48

    CPC classification number: H01L24/83 ,  H01L24/29 ,  H01L2224/29011 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

    Abstract: A preformed adhesive layer for joining components within integrated circuit packaging includes venting slots for controlling the size and location of voids within an assembled integrated circuit package. Air randomly entrapped between the surfaces of the adhesive layer and adjoining components during assembly will generally release into the venting slots during subsequent assembly and/or mounting steps performed at elevated temperatures, rather than creating internal pressures causing separation of package components or releasing into the encapsulant. Die delamination and encapsulant void problems occurring during reflow or other assembly and mounting processes as a result of entrapped air are avoided.

    Abstract translation: 用于连接集成电路封装内的部件的预成型粘合剂层包括用于控制组装的集成电路封装内的空隙的尺寸和位置的排气槽。 在组装过程中随机夹带在粘合剂层表面和相邻部件之间的空气通常在随后在高温下进行的组装和/或安装步骤期间释放到通风槽中，而不是产生导致包装部件分离或释放到密封剂中的内部压力 。 在回流或其它组装和装配过程中由于夹带空气而导致的脱模和密封剂空隙问题被避免。

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