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公开(公告)号：US11901888B1
公开(公告)日：2024-02-13
申请号：US17872125
申请日：2022-07-25
IPC分类号： H03K17/687 , H03K5/24
CPC分类号： H03K17/687 , H03K5/24
摘要： A gate charge profiler for a power transistor may include a voltage comparator unit and a timer unit. An input signal may control a gate drive current input to a gate of the power transistor to control conduction between a drain and a source of the power transistor. The voltage comparator unit may be configured to compare an input voltage and a threshold voltage, and to output a comparison signal. The input voltage may be a drain-source voltage across the drain and the source of the power transistor or a gate-source voltage across the gate and the source of the power transistor. The timer unit may be configured to output a time value based on input of a transition of the input signal and input of the comparison signal.
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42.发明授权公开(公告)号：US11901355B2
公开(公告)日：2024-02-13
申请号：US18085756
申请日：2022-12-21
发明人： Gerhard Noebauer , Florian Gasser
CPC分类号： H01L27/0629 , H01L29/0646 , H01L29/0696 , H01L29/7815
摘要： In an embodiment, a semiconductor device includes: a main transistor having a load path; a sense transistor configured to sense a main current flowing in the load path of the main transistor; and a bypass diode structure configured to protect the sense transistor and electrically coupled in parallel with the sense transistor. A sense transistor cell of the sense transistor includes a sense trench and a sense mesa. The sense trench and a bypass diode trench of the bypass diode structure form a common trench. The sense mesa and a bypass diode mesa of the bypass diode structure form a common mesa.
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43.发明公开公开(公告)号：US20240047517A1
公开(公告)日：2024-02-08
申请号：US17882064
申请日：2022-08-05
IPC分类号： H01L29/06 , H01L29/78 , H01L29/10 , H01L29/40 , H01L21/265 , H01L21/266 , H01L29/66
CPC分类号： H01L29/0634 , H01L29/7813 , H01L29/1095 , H01L29/407 , H01L21/26513 , H01L21/266 , H01L29/66734 , H01L29/1608
摘要： A power semiconductor device includes: trench gate structures in an active cell region of a semiconductor substrate and extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; an electrically insulating material covering the trench gate structures; first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region; second contact openings in the electrically insulating material vertically aligned with the trench gate structures in the inactive cell region; first counter-doped regions between the adjacent trench gate structures in the active cell region and vertically aligned with the first contact openings; second counter-doped regions underneath the trench gate structures in the inactive cell region and vertically aligned with the second contact openings; first contacts in the first contact openings; and second contacts in the second contact openings. Methods of producing the power semiconductor device are also described.
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公开(公告)号：US20240047431A1
公开(公告)日：2024-02-08
申请号：US18381929
申请日：2023-10-19
IPC分类号： H01L25/07 , H01L23/48 , H01L23/498 , H01L23/538 , H01L23/00
CPC分类号： H01L25/072 , H01L23/481 , H01L23/49822 , H01L23/5383 , H01L24/06 , H01L24/08 , H01L2224/06181 , H01L2224/08235 , H01L2924/13091
摘要： A method of forming a semiconductor module comprises forming a laminate structure having an electrically insulating core layer with opposing first and second sides, a first redistribution layer arranged on the first side and a second redistribution layer arranged on the second side. First and second transistor devices are coupled to form a half-bridge circuit. Bots transistor devices have a first side at which a cell field is arranged and an opposing second side. A control chip has a first side with contact pads. The transistor devices and control chip are arranged laterally adjacent one another and embedded in the core layer. The first side of the control chip and one transistor device and the second side of the other transistor device face towards the first redistribution layer on the first side of the core layer.
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公开(公告)号：US20240038714A1
公开(公告)日：2024-02-01
申请号：US18378733
申请日：2023-10-11
发明人： Alexander Heinrich
IPC分类号： H01L23/00
CPC分类号： H01L24/32 , H01L24/83 , H01L2224/32503 , H01L2224/8381 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01031 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/3512
摘要： A method for fabricating a semiconductor device includes providing a die with a metallization layer including a first metal with a high melting point; providing a die carrier including a second metal with a high melting point; providing a solder material including a third metal with a low melting point; providing a layer of a fourth metal with a high melting point on the semiconductor die or the die carrier; and soldering the semiconductor die to the die carrier and creating: a first intermetallic compound between the semiconductor die and the die carrier and including the first metal and the third metal; a second intermetallic compound between the first intermetallic compound and the die carrier and including the second metal and the third metal; and precipitates of a third intermetallic compound between the first intermetallic compound and the second intermetallic compound and including the third metal and the fourth metal.
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46.发明公开公开(公告)号：US20240030502A1
公开(公告)日：2024-01-25
申请号：US18332330
申请日：2023-06-09
发明人： Christian Ranacher , Evelyn Napetschnig , Sandra Ebner , Mark Pavier , Stanislav Vitanov , Paul Frank
IPC分类号： H01M10/42 , H01L23/29 , H01L21/768
CPC分类号： H01M10/425 , H01L23/293 , H01L21/76895 , H01M2010/4271 , H01L2924/181 , H01L2924/01029
摘要： In an embodiment, a semiconductor device is provided that includes a semiconductor die having a front side, a rear side opposing the front side, and side faces, a first transistor device having a first source pad and a first gate pad on the front side, and a second transistor device having a second source pad and a second gate pad on the front side. The first and second transistor devices each have a drain that is electrically coupled to a common drain pad on the rear side of the semiconductor die. The drain pad has an upper surface and side faces and at least a central portion of the upper surface is covered by a first electrically insulating layer.
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47.发明公开公开(公告)号：US20240030111A1
公开(公告)日：2024-01-25
申请号：US18351170
申请日：2023-07-12
IPC分类号： H01L23/495 , H01L21/56 , H01L23/12
CPC分类号： H01L23/49575 , H01L21/565 , H01L23/49562 , H01L23/12 , H01L23/49503 , H01L23/49537
摘要： A semiconductor package includes low voltage and high voltage contact pads, an output contact pad, a half-bridge circuit, and first, second and third leads. The half bridge circuit includes first and second transistor devices coupled in series at an output node. Both transistor devices have a first major surface which extends substantially perpendicularly to the low voltage contact pad, the high voltage contact pad, and the output contact pad. Both transistor devices are arranged in a device portion of the package and are mounted on a first lead, the first lead providing the output contact pad and being arranged on a first side of the device portion. The second and third leads are arranged in a common plane on a second side of the device portion that opposes the first side. The second lead provides the low voltage pad and the third second lead provides the high voltage output pad.
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公开(公告)号：US20230411060A1
公开(公告)日：2023-12-21
申请号：US17844524
申请日：2022-06-20
CPC分类号： H01F17/0013 , H01F27/2804 , H01F2027/2809
摘要： A semiconductor die includes: a semiconductor substrate; a transmitter or receiver circuit in the semiconductor substrate; a multi-layer stack on the semiconductor substrate, the multi-layer stack including a plurality of metallization layers separated from one another by an interlayer dielectric; and a transformer in the multi-layer stack and electrically coupled to the transmitter or receiver circuit. The transformer includes a first winding formed in a first metallization layer of the plurality of metallization layers and a second winding formed in a second metallization layer of the plurality of metallization layers. The first winding and the second winding are inductively coupled to one another. A magnetic material in the multi-layer stack is adjacent to at least part of the transformer.
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49.发明授权公开(公告)号：US11848379B2
公开(公告)日：2023-12-19
申请号：US17482490
申请日：2021-09-23
发明人： Ralf Siemieniec , David Laforet , Cédric Ouvrard
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/1095 , H01L29/407
摘要： A vertical power semiconductor transistor device includes: a drain region of a first conductivity type; a body region of a second conductivity type; a drift region of the first conductivity type which separates the body region from the drain region; a source region of the first conductivity type separated from the drift region by the body region; a gate trench extending through the source and body regions and into the drift region, the gate trench including a gate electrode; and a field electrode in the gate trench or in a separate trench. The drift region has a generally linearly graded first doping profile which increases from the body region toward a bottom of the trench that includes the field electrode, and a graded second doping profile that increases at a greater rate than the first doping profile from an end of the first doping profile toward the drain region.
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公开(公告)号：US11848243B2
公开(公告)日：2023-12-19
申请号：US17193737
申请日：2021-03-05
发明人： Man Kyo Jong , Joon Seo Son
IPC分类号： H01L23/31 , H01L21/56 , H01L21/78 , H01L23/495
CPC分类号： H01L23/31 , H01L21/561 , H01L21/565 , H01L21/78 , H01L23/49575
摘要： A molded semiconductor package includes: semiconductor dies attached to a first side of a leadframe and electrically interconnected to form a power electronic circuit; a substrate attached to a second side of the leadframe opposite the first side, and including a metal body and electrically insulative material that separates the metal body from the leadframe; and a molding compound encapsulating the dies. The metal body includes a first surface in contact with the electrically insulative material, a second surface opposite the first surface and which is not covered by the molding compound, and a bevelled edge extending between the first and second surfaces. The bevelled edge of the metal body has a first sloped side face that extends from the first surface to an apex of the bevelled edge, and a second sloped side face that extends from the apex to the second surface. Methods of producing the package are also described.
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