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    Methods for preparing a semiconductor assembly
    41.
    发明授权
    Methods for preparing a semiconductor assembly 有权
    半导体组件的制备方法

    公开(公告)号：US07256101B2

    公开(公告)日：2007-08-14

    申请号：US10893596

    申请日：2004-07-15

    Applicant: Fabrice Letertre ,  Bruno Ghyselen ,  Olivier Rayssac

    Inventor： Fabrice Letertre ,  Bruno Ghyselen ,  Olivier Rayssac

    IPC: H01L21/30 ,  H01L21/46

    CPC classification number: H01L21/76254 ,  H01L21/0445 ,  H01L21/187 ,  H01L21/7602 ,  H01L33/0012 ,  H01L33/0029

    Abstract: Methods for preparing a semiconductor assembly are disclosed. In an implementation, the technique includes providing a support substrate and a bonding surface thereon, providing a donor substrate having a weakened zone that defines a useful layer and a bonding surface on the useful layer, and providing an interface layer of a predetermined material on the bonding surface of either the support substrate or the useful layer to provide a bonding surface thereon. The method also includes molecularly bonding the bonding surface of the interface layer to the bonding surface of the other of the support substrate or the useful layer to form a separable bonding interface therebetween, and to thus form the semiconductor assembly, and heat treating the semiconductor assembly to a temperature of at least 1000 to 1100° C. without substantially increasing molecular bonding between the bonding surface of the interface layer and the bonding surface of the other of the support substrate or the useful layer, so that the separable bonding interface maintains a sufficiently weak bond that can later be overcome by applying stresses to detach the useful layer from the donor substrate.

    Abstract translation: 公开了制备半导体组件的方法。 在一个实施方案中，该技术包括在其上提供支撑衬底和结合表面，提供施主衬底，其具有限定可用层的弱化区和在有用层上的结合表面，以及在有用层上提供预定材料的界面层 粘合表面，以在其上提供粘合表面。 该方法还包括将界面层的结合表面分别结合到支撑衬底或有用层中的另一个的接合表面，以在其之间形成可分离的接合界面，从而形成半导体组件，并对半导体组件进行热处理 达到至少1000〜1100℃的温度，而不会在界面层的接合面与支撑基板或有用层的另一方的接合面之间基本上增加分子接合，使得可分离的接合界面保持足够的 弱键可以随后通过施加应力来克服有用层与施主衬底的分离。

    DEVICE AND METHOD FOR CUTTING AN ASSEMBLY
    42.
    发明申请
    DEVICE AND METHOD FOR CUTTING AN ASSEMBLY 有权
    用于切割组件的装置和方法

    公开(公告)号：US20070148915A1

    公开(公告)日：2007-06-28

    申请号：US11681349

    申请日：2007-03-02

    Applicant: Olivier Rayssac ,  Fabrice Letertre

    Inventor： Olivier Rayssac ,  Fabrice Letertre

    IPC: H01L21/46

    CPC classification number: B28D5/0011 ,  B28D5/0023 ,  B28D5/0052 ,  B28D5/0064 ,  H01L21/2007 ,  H01L21/76254 ,  Y10T83/364 ,  Y10T156/1126 ,  Y10T156/1184 ,  Y10T156/1928 ,  Y10T156/1967 ,  Y10T156/1972

    Abstract: A method is presented for cutting an assembly that includes two layers of material having a first surface and a second surface. The method includes providing a weakened interface between the two layers that defines an interface ring about the periphery of the assembly, providing a high-pressure zone at the interface ring, and providing at least one controllable low-pressure zone in the vicinity of at least one of the first surface and the second surface. The technique also includes supplying the high-pressure zone with a controllable high-pressure force, and attacking the interface ring with at least one mechanical force in combination with the high-pressure force to cut the assembly.

    Abstract translation: 提出了一种用于切割包括具有第一表面和第二表面的两层材料的组件的方法。 该方法包括在两个层之间提供弱化的界面，其限定围绕组件的周边的界面环，在界面环处提供高压区，并且在至少附近提供至少一个可控制的低压区 第一表面和第二表面之一。 该技术还包括向高压区域供应可控的高压力，并且以至少一个机械力与高压力结合来对接口环进行攻击以切割组件。

    Method of fabricating substrates and substrates obtained by this method
    44.
    发明授权
    Method of fabricating substrates and substrates obtained by this method 有权
    通过该方法制造基板和基板的方法

    公开(公告)号：US07221038B2

    公开(公告)日：2007-05-22

    申请号：US11057171

    申请日：2005-02-15

    Applicant: André Auberton-Herve

    Inventor： André Auberton-Herve

    IPC: H01L29/06

    CPC classification number: H01L21/76254

    Abstract: Techniques are shown in which substrates having a first layer of a first material and second layer of a second material, wherein the second material is less noble than the first material, is provided by bonding the first and second layers together with an amorphous layer interposed there between. The amorphous material may be deposited on a bonding face of the first layer, second layer, or both, before the operation of bonding the first and second layers. The layer with less noble material may be a supporting layer and the other layer may be an active layer for forming components in optics, electronics, or opto-electronics. The amorphous layer may be polished before the bonding operation.

    Abstract translation: 示出了其中具有第一材料的第一层和第二材料的第二层的衬底（其中第二材料比第一材料更不贵）的衬底是通过将第一和第二层与插入其中的非晶层接合而提供的 之间。 在结合第一层和第二层的操作之前，非晶材料可以沉积在第一层，第二层或两者的接合面上。 具有较低贵重材料的层可以是支撑层，另一层可以是用于在光学，电子学或光电子学中形成组件的有源层。 可以在接合操作之前对非晶层进行抛光。

    METHODS FOR PRODUCING A SEMICONDUCTOR ENTITY
    45.
    发明申请
    METHODS FOR PRODUCING A SEMICONDUCTOR ENTITY 有权
    生产半导体实体的方法

    公开(公告)号：US20070104240A1

    公开(公告)日：2007-05-10

    申请号：US11617025

    申请日：2006-12-28

    Applicant: Yves Le Vaillant ,  Olivier Rayssac ,  Christophe Fernandez

    Inventor： Yves Le Vaillant ,  Olivier Rayssac ,  Christophe Fernandez

    IPC: H01S5/00

    CPC classification number: H01L21/76254 ,  H01L2221/68318

    Abstract: A method for producing a semiconductor entity is described. The method includes providing a donor substrate having a zone of weakness at a predetermined depth to define a thin layer, and the donor substrate includes a bonding interface. A receiver substrate is also provided that includes at least one motif on its surface. The technique further includes bonding the donor substrate at the bonding interface to the at least one motif on the receiver substrate, and supplying sufficient energy to detach a portion of the thin layer from the donor substrate located at the at least one motif and to rupture bonds within the thin layer. The energy thus supplied is insufficient to rupture the bond at the bonding interface. Also described is fabrication of a wafer and the use of the method to produce chips suitable for use in electronics, optics, or optoelectronics applications.

    Abstract translation: 对半导体实体的制造方法进行说明。 该方法包括提供具有预定深度的弱区的施主衬底以限定薄层，并且施主衬底包括结合界面。 还提供了在其表面上包括至少一个图案的接收器衬底。 该技术还包括将接合界面处的施主衬底粘合到接收器基底上的至少一个基序上，并且提供足够的能量以将薄层的一部分从位于至少一个基序上的施主衬底分离出来，并断裂键 在薄层内。 这样提供的能量不足以破坏接合界面处的结合。 还描述了晶片的制造和使用该方法来生产适用于电子，光学或光电子应用的芯片。

    Tools and methods for disuniting semiconductor wafers
    46.
    发明授权
    Tools and methods for disuniting semiconductor wafers 有权
    用于分离半导体晶片的工具和方法

    公开(公告)号：US07187162B2

    公开(公告)日：2007-03-06

    申请号：US10733470

    申请日：2003-12-12

    Applicant: Sebastien Kerdiles ,  Yves-Mathieu Le Vaillant

    Inventor： Sebastien Kerdiles ,  Yves-Mathieu Le Vaillant

    IPC: G01R31/28

    CPC classification number: H01L21/68707 ,  G01N19/04 ,  H01L21/67092 ,  Y10S156/943 ,  Y10T29/53683 ,  Y10T83/0267 ,  Y10T156/1132 ,  Y10T156/1168 ,  Y10T156/1978 ,  Y10T156/1983

    Abstract: A tool for disuniting two wafers, at least one of which is for use in fabricating substrates for microelectronics, optoelectronics, or optics, the tool comprising two gripper members suitable for being fixed temporarily to respective opposite faces of the two wafers that are united with each other, and a disuniting control device suitable for moving said members relative to each other. The tool is remarkable in that the disuniting control device comprises an actuator for positively displacing said gripper members and for inducing controlled flexing in at least one of said members. This makes it easier to disunite the wafers while reducing the risk of damaging them. The invention is applicable to disuniting wafers that have been weakened by implantation, that have been temporarily bonded together, etc.

    Abstract translation: 用于分离两个晶片的工具，其中至少一个用于制造用于微电子学，光电子学或光学器件的衬底，该工具包括两个夹持器构件，其适于临时固定在两个晶片的相应的相对面上 以及适于相对于彼此移动所述构件的分离控制装置。 该工具是显着的，因为分离控制装置包括用于使所述夹持构件正向移动并用于在至少一个所述构件中引起受控弯曲的致动器。 这使得更容易使晶片脱粒，同时降低了损坏晶片的风险。 本发明适用于已经被临时粘合在一起的通过植入而被削弱的晶片的分离等。

    Preventive treatment method for a multilayer semiconductor structure
    48.
    发明授权
    Preventive treatment method for a multilayer semiconductor structure 有权
    多层半导体结构的预防处理方法

    公开(公告)号：US07169683B2

    公开(公告)日：2007-01-30

    申请号：US10686082

    申请日：2003-10-14

    Applicant: Bruno Ghyselen ,  Olivier Rayssac

    Inventor： Bruno Ghyselen ,  Olivier Rayssac

    IPC: H01L21/48

    CPC classification number: H01L21/76259 ,  H01L21/76254

    Abstract: A preventive treatment method for a multilayer semiconductor structure having a support substrate, at least one intermediate layer and a surface layer in which the surface layer is to be subjected to a subsequent chemical treatment. The method includes forming a protective layer between the intermediate layer and the surface layer. The protective layer is made from a material chosen to be sufficiently resistant to the chemical treatment to protect the intermediate layer from chemical attack.

    Abstract translation: 一种多层半导体结构的预防处理方法，其具有支撑基板，至少一个中间层和表面层，其中表面层将进行后续的化学处理。 该方法包括在中间层和表面层之间形成保护层。 保护层由选择为具有足够抗化学处理的材料制成，以保护中间层免受化学侵蚀。

    Method for heat treating a semiconductor wafer
    50.
    发明授权
    Method for heat treating a semiconductor wafer 有权
    半导体晶片热处理方法

    公开(公告)号：US07098148B2

    公开(公告)日：2006-08-29

    申请号：US10863352

    申请日：2004-06-09

    Applicant: Walter Schwarzenbach ,  Jean-Marc Waechter

    Inventor： Walter Schwarzenbach ,  Jean-Marc Waechter

    IPC: H01L21/31 ,  H01L21/469 ,  H01L21/30 ,  H01L21/46 ,  H01L21/332

    CPC classification number: H01L21/76251 ,  H01L21/2007 ,  H01L21/324

    Abstract: A method for heat treatment of a semiconductor wafer placed on a support. The method includes subjecting the wafer to a heat treatment with a slow temperature rise from an initial temperature to a treatment ending temperature, and minimizing slip lines that would otherwise result in the wafer from the heat treatment by introducing at least one temperature plateau of constant temperature and of predetermined duration in the heat treatment before reaching the treatment ending temperature. The method reduces the temperature gradients on the wafer to minimize slip lines in the wafer resulting from the heat treatment.

    Abstract translation: 一种用于热处理放置在支撑体上的半导体晶片的方法。 该方法包括使晶片经历从初始温度到处理结束温度的缓慢温度升高的热处理，并且最小化滑移线，否则将导致晶片从热处理引入至少一个恒定温度的平台 并且在达到治疗结束温度之前的热处理中具有预定的持续时间。 该方法降低晶片上的温度梯度以最小化由热处理产生的晶片的滑移线。

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