公开(公告)号：US07959984B2

公开(公告)日：2011-06-14

申请号：US11022982

申请日：2004-12-22

Applicant: Shrikant P. Lohokare ,  Andrew D. Bailey, III

Inventor： Shrikant P. Lohokare ,  Andrew D. Bailey, III

IPC: H05H1/24

CPC classification number: H01J37/32633 ,  C23C16/4404 ,  H01J37/32623

Abstract: In a plasma processing system, a method of reducing byproduct deposits on a set of plasma chamber surfaces of a plasma processing chamber is disclosed. The method includes providing a deposition barrier in the plasma processing chamber, the deposition barrier is configured to be disposed in a plasma generating region of the plasma processing chamber, thereby permitting at least some process byproducts produced when a plasma is struck within the plasma processing chamber to adhere to the deposition barrier and reducing the byproduct deposits on the set of plasma processing chamber surfaces.

Abstract translation: 在等离子体处理系统中，公开了一种在等离子体处理室的一组等离子体室表面上减少副产物沉积的方法。 所述方法包括在所述等离子体处理室中设置沉积阻挡层，所述沉积阻挡层被配置为设置在所述等离子体处理室的等离子体产生区域中，从而允许在所述等离子体处理室内等离子体被击中时产生的至少一些过程副产物 以附着到沉积屏障上并减少等离子体处理室表面组上的副产物沉积物。

公开(公告)号：US20110108524A1

公开(公告)日：2011-05-12

申请号：US12872982

申请日：2010-08-31

Applicant: Rajinder Dhindsa ,  Michael C. Kellogg ,  Babak Kadkhodayan ,  Andrew D. Bailey, III

Inventor： Rajinder Dhindsa ,  Michael C. Kellogg ,  Babak Kadkhodayan ,  Andrew D. Bailey, III

IPC: C23F1/00 ,  H01L21/3065 ,  C23F1/08

CPC classification number: H01J37/32642 ,  H01J37/32623

Abstract: An arrangement for performing pressure control within a processing chamber substrate processing is provided. The arrangement includes a peripheral ring configured at least for surrounding a confined chamber volume that is configured for sustaining a plasma for etching the substrate during substrate processing. The peripheral ring includes a plurality of slots that is configured at least for exhausting processed byproduct gas from the confined chamber volume during substrate processing. The arrangement also includes a conductive control ring that is positioned next to the peripheral ring and is configured to include plurality of slots. The pressure control is achieved by moving the conductive control ring relative to the peripheral ring such that a first slot on the peripheral ring and a second slot on the conductive control ring are offset with respect to one another in a range of zero offset to full offset.

Abstract translation: 提供了一种用于在处理室衬底处理中执行压力控制的装置。 该装置包括至少围绕限制室容积配置的外围环，该限定室容积被配置为在衬底处理期间维持用于刻蚀衬底的等离子体。 周边环包括多个狭槽，其被构造成至少在衬底处理期间从受限腔体积中排出经处理的副产物气体。 该布置还包括导电控制环，该导电控制环位于外围环旁边并且被配置为包括多个狭槽。 通过相对于外围环移动导电控制环来实现压力控制，使得外围环上的第一槽和导电控制环上的第二槽相对于彼此在零偏移到全偏移的范围内彼此偏移 。

公开(公告)号：US20100096087A1

公开(公告)日：2010-04-22

申请号：US12647301

申请日：2009-12-24

Applicant: Gregory S. Sexton ,  Andrew D. Bailey, III ,  Alan M. Schoepp ,  John D. Boniface

Inventor： Gregory S. Sexton ,  Andrew D. Bailey, III ,  Alan M. Schoepp ,  John D. Boniface

IPC: H01L21/306

CPC classification number: H01L21/67069 ,  H01J37/32568

Abstract: Positional relationships are established in a process chamber. A base is configured with a lower electrode surface to support a wafer, and an upper electrode has a lower surface. A drive mounted on the base has a linkage connected to the upper electrode. A fixture placed on the lower surface moves into a desired orientation of the lower electrode. With the upper electrode loosely connected by the linkage to the drive, the fixture transfers the desired orientation to the upper electrode. The linkage is tightened to maintain the desired orientation, the fixture is removed and a process exclusion insert is mounted to the upper electrode. The drive moves the upper electrode and the insert to define an inactive process zone between the upper electrode and the wafer on the lower electrode to protect a central area of the wafer during etching of a wafer edge environ around the central area.

Abstract translation: 位置关系建立在一个过程室中。 基底配置有下电极表面以支撑晶片，并且上电极具有下表面。 安装在基座上的驱动器具有连接到上电极的连杆。 放置在下表面上的固定器移动到下电极的期望取向。 通过与驱动器的联动松动地连接上电极，固定装置将期望的方向传送到上电极。 连接件被拧紧以保持所需的取向，夹具被移除，并且将过程排除插入件安装到上电极。 驱动器移动上电极和插入件以在下电极上的上电极和晶片之间限定非活动的工艺区域，以在蚀刻围绕中心区域的晶片边缘环境时保护晶片的中心区域。

公开(公告)号：US07653515B2

公开(公告)日：2010-01-26

申请号：US11698400

申请日：2007-01-25

Applicant: Puneet Yadav ,  Andrew D. Bailey, III

Inventor： Puneet Yadav ,  Andrew D. Bailey, III

IPC: G06F19/00

CPC classification number: G05B19/41875 ,  G05B2219/31352 ,  G05B2219/32191 ,  Y02P90/22

Abstract: A method for adjusting a data set defining a set of process runs, each process run having a set of data corresponding to a set of variables for a wafer processing operation is provided. A model derived from a data set is received. A new data set corresponding to one process run is received. The new data set is projected to the model. An outlier data point produced as a result of the projecting is identified. A variable corresponding to the one outlier data point is identified, the identified variable exhibiting a high contribution. A value for the variable from the new data set is identified. Whether the value for the variable is unimportant is determined. A normalized matrix of data is created, using random data and the variable that was determined to be unimportant from each of the new data set and the data set. The data set is updated with the normalized matrix of data.

Abstract translation: 提供一种用于调整定义一组处理运行的数据集的方法，每个处理运行具有与用于晶片处理操作的一组变量相对应的一组数据。 接收从数据集导出的模型。 接收对应于一个进程运行的新数据集。 新数据集投影到模型中。 识别作为投影结果产生的异常值数据点。 识别与一个异常数据点对应的变量，所识别的变量表现出高贡献。 识别来自新数据集的变量的值。 确定变量的值是否不重要。 使用随机数据和被确定为与每个新数据集和数据集不重要的变量来创建数据的归一化矩阵。 数据集用数据的归一化矩阵更新。

公开(公告)号：US20090170334A1

公开(公告)日：2009-07-02

申请号：US12341384

申请日：2008-12-22

Applicant: Tong Fang ,  Andrew D. Bailey, III ,  Yunsang Kim ,  Olivier Rigoutat ,  George Stojakovic

Inventor： Tong Fang ,  Andrew D. Bailey, III ,  Yunsang Kim ,  Olivier Rigoutat ,  George Stojakovic

IPC: H01L21/3065

CPC classification number: H01L21/3065 ,  H01J37/32366 ,  H01L21/02068 ,  H01L21/02087 ,  H01L21/32136 ,  H01L21/6708

Abstract: A method of bevel edge etching a semiconductor substrate having exposed copper surfaces with a fluorine-containing plasma in a bevel etcher in which the semiconductor substrate is supported on a semiconductor substrate support comprises bevel edge etching the semiconductor substrate with the fluorine-containing plasma in the bevel etcher; evacuating the bevel etcher after the bevel edge etching is completed; flowing defluorinating gas into the bevel etcher; energizing the defluorinating gas into a defluorination plasma at a periphery of the semiconductor substrate; and processing the semiconductor substrate with the defluorination plasma under conditions to prevent discoloration of the exposed copper surfaces of the semiconductor substrate upon exposure, the discoloration occurring upon prolonged exposure to air.

Abstract translation: 在半导体衬底支撑在半导体衬底支撑体上的斜面蚀刻器中，使用具有含氟等离子体的具有暴露的铜表面的半导体衬底进行斜边蚀刻的方法包括：在半导体衬底支撑体中的含氟等离子体 斜角蚀刻机 在斜边蚀刻完成之后排空斜面蚀刻机; 将脱氟气体流入斜面蚀刻机; 在所述半导体衬底的外围将所述脱氟气体通电为脱氟等离子体; 并且在曝光时防止半导体衬底的暴露的铜表面的变色的条件下，用脱氟等离子体处理半导体衬底，在长时间暴露于空气时发生变色。

公开(公告)号：US07540935B2

公开(公告)日：2009-06-02

申请号：US11076725

申请日：2005-03-09

Applicant: Yunsang Kim ,  Andrew D. Bailey, III ,  Hyungsuk Alexander Yoon ,  Arthur M. Howald

Inventor： Yunsang Kim ,  Andrew D. Bailey, III ,  Hyungsuk Alexander Yoon ,  Arthur M. Howald

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/32136 ,  H01L21/31683 ,  H01L21/321 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/32138 ,  H01L21/32139 ,  H01L21/7684 ,  H01L21/76865 ,  H01L21/76885

Abstract: A method of etching a conductive layer includes converting at least a portion of the conductive layer and etching the conductive layer to substantially remove the converted portion of the conductive layer and thereby expose a remaining surface. The remaining surface has an average surface roughness of less than about 10 nm. A system for etching a conductive layer is also disclosed.

Abstract translation: 蚀刻导电层的方法包括转换导电层的至少一部分并蚀刻导电层，以基本上去除导电层的转换部分，从而暴露出剩余的表面。 剩余的表面具有小于约10nm的平均表面粗糙度。 还公开了用于蚀刻导电层的系统。

公开(公告)号：US07282909B2

公开(公告)日：2007-10-16

申请号：US11172017

申请日：2005-06-29

Applicant: Andrew D. Bailey, III

Inventor： Andrew D. Bailey, III

IPC: G01B7/06 ,  G01R33/12

CPC classification number: G01B7/105 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of determining the thickness of a conductive film is disclosed. The method employs measured voltage and current responses that have been temperature-compensated to determine the thickness of the conductive film. The temperature compensation uses a temperature compensation factor obtained from a calibration substrate different from the target substrate on which the conductive film being measured is disposed. The calibration substrate has a conductive film formed of a conductive material that is substantially similar to the conductive material of the target substrate.

Abstract translation: 公开了确定导电膜厚度的方法。 该方法采用经过温度补偿的测量电压和电流响应来确定导电膜的厚度。 温度补偿使用从与其上设置有测量导电膜的目标衬底不同的校准衬底获得的温度补偿因子。 校准基板具有由导电材料形成的导电膜，其基本上类似于目标基板的导电材料。

公开(公告)号：US06939796B2

公开(公告)日：2005-09-06

申请号：US10390117

申请日：2003-03-14

Applicant: Shrikant P. Lohokare ,  Andrew D. Bailey, III ,  David Hemker ,  Joel M. Cook

Inventor： Shrikant P. Lohokare ,  Andrew D. Bailey, III ,  David Hemker ,  Joel M. Cook

IPC: B44C1/22 ,  H01L20060101 ,  H01L21/302 ,  H01L21/304 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/4763 ,  H01L21/768 ,  H01L33/00

CPC classification number: H01L21/7684 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/32136

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

Abstract translation: 用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底。 图案化半导体衬底具有填充图案中的多个特征的导电互连材料。 导电互连材料具有覆盖层部分。 覆盖层部分具有局部不均匀性。 去除覆盖层部分的大部分以平坦化上覆层部分。 映射基本上局部平坦化的覆盖层部分以确定全局不均匀性。 基本上局部平坦化的覆盖层部分被蚀刻以基本上去除全局不均匀性。

公开(公告)号：US06341574B1

公开(公告)日：2002-01-29

申请号：US09439661

申请日：1999-11-15

Applicant: Andrew D. Bailey, III ,  Alan M. Schoepp ,  David J. Hemker ,  Mark H. Wilcoxson ,  Andras Kuthi

Inventor： Andrew D. Bailey, III ,  Alan M. Schoepp ,  David J. Hemker ,  Mark H. Wilcoxson ,  Andras Kuthi

IPC: C23C1600

CPC classification number: H01J37/32623 ,  H01J37/3266

Abstract: A plasma processing system for processing a substrate which includes a single chamber, substantially azimuthally symmetric plasma processing chamber within which a plasma is both ignited and sustained for the processing. The plasma processing chamber has no separate plasma generation chamber. The plasma processing chamber has an upper end and a lower end. The plasma processing system includes a coupling window disposed at an upper end of the plasma processing chamber and an RF antenna arrangement disposed above a plane defined by the substrate when the substrate is disposed within the plasma processing chamber for the processing. The plasma processing system also includes an electromagnet arrangement disposed above the plane defined by the substrate. The electromagnet arrangement is configured so as to result in a radial variation in the controllable magnetic field within the plasma processing chamber in the region proximate the coupling window and antenna when at least one direct current is supplied to the electromagnet arrangement. The radial variation is effective to affect processing uniformity across the substrate. The plasma processing system additionally includes a dc power supply coupled to the electromagnet arrangement. The dc power supply has a controller to vary a magnitude of at least one direct current, thereby changing the radial variation in the controllable magnetic field within the plasma processing chamber in the region proximate the antenna to improve the processing uniformity across the substrate.

Abstract translation: 一种用于处理衬底的等离子体处理系统，其包括单室，基本方位对称的等离子体处理室，其中等离子体都被点燃并持续进行处理。 等离子体处理室没有单独的等离子体产生室。 等离子体处理室具有上端和下端。 等离子体处理系统包括设置在等离子体处理室的上端的耦合窗口和当衬底设置在等离子体处理室内用于处理时设置在由衬底限定的平面上方的RF天线布置。 等离子体处理系统还包括设置在由衬底限定的平面之上的电磁体装置。 当至少一个直流电被提供给电磁体装置时，电磁体装置构造成导致等离子体处理室内的可耦合窗口和天线附近的区域内的可控磁场的径向变化。 径向变化对影响衬底上的加工均匀性是有效的。 等离子体处理系统还包括耦合到电磁体装置的直流电源。 直流电源具有控制器来改变至少一个直流电流的大小，从而改变等离子体处理室内靠近天线的可控磁场中的径向变化，以改善穿过衬底的加工均匀性。

公开(公告)号：US06320320B1

公开(公告)日：2001-11-20

申请号：US09440418

申请日：1999-11-15

Applicant: Andrew D. Bailey, III ,  Alan M. Schoepp ,  Andras Kuthi

Inventor： Andrew D. Bailey, III ,  Alan M. Schoepp ,  Andras Kuthi

IPC: H01J724

CPC classification number: H01J37/32467 ,  H01J37/321

Abstract: A plasma processing apparatus for processing a substrate with a plasma is disclosed. The apparatus includes a first RF power source having a first RF frequency, and a process chamber. Further, the apparatus includes a substantially circular antenna operatively coupled to the first RF power source and disposed above a plane defined by the substrate when the substrate is disposed within the process chamber for processing. The substantially circular antenna being configured to induce an electric field inside the process chamber with a first RF energy generated by the first RF power source. The substantially circular antenna including at least a first pair of concentric loops in a first plane and a second pair of concentric loops in a second plane. The first pair of concentric loops and the second pair of concentric loops being substantially identical and symmetrically aligned with one another. The substantially circular antenna forming an azimuthally symmetric plasma inside the process chamber. The apparatus also includes a coupling window disposed between the antenna and the process chamber. The coupling window being configured to allow the passage of the first RF energy from the antenna to the interior of the process chamber. The coupling window having a first layer and a second layer. The second layer being configured to substantially suppress the capacitive coupling formed between the substantially circular antenna and the plasma. The substantially circular antenna and the coupling window working together to produce a substantially uniform process rate across the surface of the substrate.

Abstract translation: 公开了一种用等离子体处理衬底的等离子体处理装置。 该装置包括具有第一RF频率的第一RF电源和处理室。 此外，该设备包括可操作地耦合到第一RF电源并且当基板设置在处理室内以进行处理时设置在由基板限定的平面之上的基本圆形的天线。 基本上圆形的天线被配置为利用由第一RF电源产生的第一RF能量来诱导处理室内的电场。 基本上圆形的天线包括第一平面中的至少第一对同心环和在第二平面中的第二对同心环。 第一对同心环和第二对同心环彼此基本相同和对称地对准。 大致圆形天线在处理室内形成方位对称等离子体。 该装置还包括设置在天线和处理室之间的耦合窗口。 耦合窗口被配置为允许第一RF能量从天线通过到处理室的内部。 耦合窗具有第一层和第二层。 第二层被配置为基本上抑制形成在基本上圆形的天线和等离子体之间的电容耦合。 基本上圆形的天线和耦合窗口一起工作，以在衬底的表面上产生基本均匀的工艺速率。