公开(公告)号：US08971395B2

公开(公告)日：2015-03-03

申请号：US13293513

申请日：2011-11-10

Applicant: Ming-Chieh Huang ,  Jing Jing Chen ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Ming-Chieh Huang ,  Jing Jing Chen ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03566 ,  H04L2025/03617 ,  H04L2025/03687

Abstract: A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel.

Abstract translation: 具有可编程抽头的判决反馈均衡器（DFE）包括一个加法器，用于接收DFE输入信号。 延迟元素与夏天相结合。 延迟元件串联连接。 每个延迟元件向延迟元件提供输入信号的相应延迟信号。 重量发生器被配置成提供抽头重量。 DFE被配置为将每个抽头权重乘以来自相应延迟元件的相应延迟信号以提供抽头输出。 基于第一阈值和对应于各抽头输出的每个脉冲响应或每个抽头权重的第一比较，每个抽头输出被选择性地被加到加法器或禁止中，其中脉冲响应是响应中的DFE输入信号 通过通道传输的脉冲信号。

公开(公告)号：US08698566B2

公开(公告)日：2014-04-15

申请号：US13252498

申请日：2011-10-04

Applicant: Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Fu-Lung Hsueh ,  Yuwen Swei

Inventor： Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Fu-Lung Hsueh ,  Yuwen Swei

IPC: H03L7/085 ,  H03L7/10 ,  H03B5/12

CPC classification number: H03L7/102 ,  H03L7/099 ,  H03L2207/06

Abstract: An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.

Abstract translation: 电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。 校准电路包括两个比较器，并向LCVCO提供粗调信号。 两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。 校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。 环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。 粗调频率范围大于微调频率范围。

公开(公告)号：US08643422B1

公开(公告)日：2014-02-04

申请号：US13547396

申请日：2012-07-12

Applicant: Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Derek C. Tao

Inventor： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Derek C. Tao

IPC: H03K3/356

CPC classification number: H03K5/08 ,  H03K3/356139 ,  H04L27/01

Abstract: This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.

Abstract translation: 该描述涉及包括第一锁存器的限幅器。 第一锁存器包括被配置为接收第一时钟信号的评估晶体管和被配置为接收第二时钟信号的显影晶体管。 第一时钟信号与第二时钟信号不同。 第一锁存器包括被配置为接收第一和第二互补输入的第一和第二输入晶体管。 第一锁存器包括配置成接收第三时钟信号的至少一个预充电晶体管。 第一锁存器还包括至少一个交叉锁存晶体管对，该至少一个交叉锁存晶体管对连接在评估晶体管与第一和第二输出节点之间。 切片器包括连接到第一和第二输出节点和第三输出节点的第二锁存器。 切片器包括连接到第三输出节点并被配置为产生最终输出信号的缓冲器。

公开(公告)号：US20130342247A1

公开(公告)日：2013-12-26

申请号：US13530136

申请日：2012-06-22

Applicant: Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Fu-Lung HSUEH

Inventor： Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Fu-Lung HSUEH

IPC: H03L7/08

CPC classification number: H03L7/103 ,  H03L7/097 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/18 ,  H03L2207/06

Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

Abstract translation: 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

公开(公告)号：US20130335145A1

公开(公告)日：2013-12-19

申请号：US13527365

申请日：2012-06-19

Applicant: Tsung-Ching HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN

Inventor： Tsung-Ching HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN

IPC: H03F3/45

CPC classification number: H03F3/082 ,  H03F1/0205 ,  H03F3/08 ,  H03F3/3022 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2200/216 ,  H03F2203/30031 ,  H03F2203/45222 ,  H03F2203/45644 ,  H03F2203/45686 ,  H03F2203/45702 ,  H03F2203/45724

Abstract: A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to be coupled to an input signal. A second inverter has a second input node and a second output node. The second input node is configured to receive a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node.

Abstract translation: 跨阻放大器包括具有第一输入节点和第一输出节点的第一反相器。 第一输入节点被配置为耦合到输入信号。 第二反相器具有第二输入节点和第二输出节点。 第二输入节点被配置为接收参考电压端子。 第一反相器和第二反相器被配置为在第一输出节点和第二输出节点之间提供差分输出电压信号。

公开(公告)号：US08575966B2

公开(公告)日：2013-11-05

申请号：US13718235

申请日：2012-12-18

Applicant: Chih-Chang Lin ,  Chan-Hong Chern ,  Steven Swei ,  Ming-Chieh Huang ,  Tien-Chun Yang

Inventor： Chih-Chang Lin ,  Chan-Hong Chern ,  Steven Swei ,  Ming-Chieh Huang ,  Tien-Chun Yang

IPC: H03D13/00 ,  H03L7/06

CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

Abstract: A method of operating a charge pump of a phase-lock assistant circuit includes determining a first relative timing relationship of a phase of a data signal to a phase of a first phase clock. A second relative timing relationship of the phase of the data signal to a phase of a second phase clock is determined, and the first and second phase clocks have a 45° phase difference. An up signal and a down signal are generated in response to the first relative timing relationship and the second relative timing relationship. The charge pump circuit is driven according to the up signal and the down signal.

Abstract translation: 操作锁相辅助电路的电荷泵的方法包括确定数据信号的相位与第一相位时钟的相位的第一相对定时关系。 确定数据信号的相位与第二相位时钟的相位的第二相对定时关系，并且第一和第二相位时钟具有45°的相位差。 响应于第一相对定时关系和第二相对定时关系产生升高信号和下降信号。 电荷泵电路根据上升信号和下降信号进行驱动。

公开(公告)号：US20130120884A1

公开(公告)日：2013-05-16

申请号：US13293853

申请日：2011-11-10

Applicant: Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H02H9/04

CPC classification number: H02H9/04 ,  H01L23/60 ,  H01L27/0248 ,  H01L2924/0002 ,  H03F2200/294 ,  H03F2203/45638 ,  H03G1/0023 ,  H03K3/35613 ,  H03K19/018514 ,  H01L2924/00

Abstract: An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition.

Abstract translation: 输入/输出（I / O）电路包括与I / O电路的输出节点电耦合的静电放电（ESD）保护电路。 至少一个电感器和至少一个负载以串联方式电耦合，并且在I / O电路的输出节点和电力线之间。 电路与所述至少一个电感器和所述至少一个负载之间的节点电耦合。 电路可操作以在信号转换期间增加流过至少一个电感器的电流。

公开(公告)号：US08432204B1

公开(公告)日：2013-04-30

申请号：US13344637

申请日：2012-01-06

Applicant: Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei ,  Fu-Lung Hsueh

IPC: H03L7/06

CPC classification number: H03L7/102 ,  H03L7/099 ,  H03L7/104

Abstract: A PLL circuit includes a phase frequency detector; a programmable charge pump coupled to an output of the phase frequency detector; a loop filter coupled to an output of the charge pump, the loop filter providing a fine tuning voltage; a first voltage-to-current converter, the first voltage-to-current converter providing a fine tuning current corresponding to the fine tuning voltage; a current-controlled oscillator (CCO); a feedback divider coupled to an output of the CCO and an input of the phase frequency detector; and an analog calibration circuit. The analog calibration circuit provides a coarse adjustment current for coarse adjustments to a frequency pivot point for an oscillator frequency of the CCO, wherein the CCO generates a frequency signal at an output responsive to a summed coarse adjustment and fine tuning current, wherein the frequency pivot point is continuously adjustable.

Abstract translation: PLL电路包括相位检波器; 耦合到所述相位频率检测器的输出的可编程电荷泵; 耦合到电荷泵的输出的环路滤波器，所述环路滤波器提供微调电压; 第一电压 - 电流转换器，第一电压 - 电流转换器提供对应于微调电压的微调电流; 电流控制振荡器（CCO）; 耦合到CCO的输出的反馈分压器和相位频率检测器的输入端; 和模拟校准电路。 模拟校准电路提供用于对CCO的振荡器频率的频率枢转点进行粗调整的粗调电流，其中CCO响应于总和的粗调和微调电流而在输出端产生频率信号，其中频率枢轴 点连续可调。

公开(公告)号：US08378654B2

公开(公告)日：2013-02-19

申请号：US12750260

申请日：2010-03-30

Applicant: Chan-Hong Chern ,  Tzu Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

Inventor： Chan-Hong Chern ,  Tzu Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

IPC: G05F1/44

CPC classification number: H02M3/158 ,  G05F1/44 ,  G05F1/56

Abstract: A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.

Abstract translation: 提供了具有高精度和电源抑制比（PSRR）的稳压电路。 在一个实施例中，具有到反相输入的电压参考输入的运算放大器具有连接到PMOS晶体管的栅极的第一输出。 PMOS晶体管的源极和漏极各自连接到电源和稳压器输出。 电压调节器输出连接到偏置在饱和模式的NMOS晶体管和一系列两个电阻。 运算放大器的非反相输入端连接在第一个反馈回路的两个电阻之间。 运算放大器的第二个输出通过用于第二反馈回路的交流耦合电容器连接到NMOS晶体管的栅极。 运算放大器的第一个输出可以通过电容连接到电源电压，以进一步提高高频PSRR。 在另一个实施例中，PMOS和NMOS晶体管的作用相反。

公开(公告)号：US20120262212A1

公开(公告)日：2012-10-18

申请号：US13084817

申请日：2011-04-12

Applicant: Chih-Chang LIN ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Tao Wen CHUNG

Inventor： Chih-Chang LIN ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Tao Wen CHUNG

IPC: H03K5/15

CPC classification number: H03K5/15013

Abstract: A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals.

Abstract translation: 多相时钟发生器包括至少一个分频器级。 时钟信号作为第一级时钟输入提供给分频器的第一级中的分频器。 第N级包括2N个分频器，其中N是正整数。 第一级中的每个分频器被配置为将第一级时钟输入的第一时钟频率除以2以提供第一级输出。 第N级中的每个除法器被配置为将输入的第N级时钟的第N个时钟频率除以2以提供第N级输出。 在第N级的分频器的第N级输出提供2N相位时钟信号，它们在相邻的相位时钟信号之间以相同的相位差均匀分布。