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    SEMICONDUCTOR MANUFACTURING USING DESIGN VERIFICATION WITH MARKERS
    41.
    发明申请
    SEMICONDUCTOR MANUFACTURING USING DESIGN VERIFICATION WITH MARKERS 审中-公开
    半导体制造使用设计验证与标记

    公开(公告)号：US20150178438A1

    公开(公告)日：2015-06-25

    申请号：US14137530

    申请日：2013-12-20

    申请人： ERTUGRUL DEMIRCAN ,  Douglas M. Reber ,  Michael A. Stockinger ,  Edward O. Travis

    发明人： ERTUGRUL DEMIRCAN ,  Douglas M. Reber ,  Michael A. Stockinger ,  Edward O. Travis

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A first circuit design is entered in an electronic design automation (EDA) computer system. The first circuit design includes a first feature with a first node. A marker is associated with the first node and represents a voltage associated with the first node as an algebraic expression of a numerical value representing a property of the circuit design. The marker is used to determine if the component of the circuit design violates a design rule.

    摘要翻译： 在电子设计自动化（EDA）计算机系统中输入第一电路设计。 第一电路设计包括具有第一节点的第一特征。 标记与第一节点相关联，并且表示与第一节点相关联的电压作为表示电路设计的属性的数值的代数表达式。 标记用于确定电路设计的组件是否违反了设计规则。

    Method and system for derived layer checking for semiconductor device design
    44.
    发明授权
    Method and system for derived layer checking for semiconductor device design 有权
    用于半导体器件设计的导出层检查的方法和系统

    公开(公告)号：US08707231B2

    公开(公告)日：2014-04-22

    申请号：US13562443

    申请日：2012-07-31

    申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    IPC分类号： G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

    CPC分类号： G06F17/5081 ,  G03F1/00 ,  G06F19/00 ,  G21K5/00

    摘要： A system and method are provided for enabling a systematic detection of issues arising during the course of mask generation for a semiconductor device. IC mask layer descriptions are analyzed and information is generated that identifies devices formed by active layers in the masks, along with a description of all layers in proximity to the found devices. The IC mask information is compared to a netlist file generated from the initial as-designed schematic. Determinations can then made, for example, as to whether all intended devices are present, any conflicting layers are in proximity to or interacting with the intended devices, and any unintended devices are present in the mask layers. Steps can then be taken to resolve the issues presented by the problematic devices.

    摘要翻译： 提供了一种系统和方法，用于能够系统地检测在半导体器件的掩模生成过程中产生的问题。 分析IC掩模层描述，并生成识别掩模中由有源层形成的设备的信息，以及邻近发现的设备的所有层的描述。 将IC掩模信息与从初始设计原理图生成的网表文件进行比较。 然后可以进行例如关于所有预期设备是否存在的确定，任何冲突的层都与预期设备接近或相互作用，并且任何非预期的设备存在于掩模层中。 然后可以采取步骤来解决有问题的设备提出的问题。

    METHOD AND APPARATUS TO IMPROVE RELIABILITY OF VIAS
    45.
    发明申请
    METHOD AND APPARATUS TO IMPROVE RELIABILITY OF VIAS 有权
    提高VIAS可靠性的方法和装置

    公开(公告)号：US20140091475A1

    公开(公告)日：2014-04-03

    申请号：US13630996

    申请日：2012-09-28

    申请人： DOUGLAS M. REBER

    发明人： DOUGLAS M. REBER

    IPC分类号： G06F17/50 ,  H01L23/48

    CPC分类号： G06F17/5068 ,  G06F2217/72 ,  H01L21/76814 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

    摘要： A semiconductor device comprising a first insulating layer, a first metal conductor layer formed over the first insulating layer, a second insulating layer comprising a low-k insulating material formed over the first metal conductor, a second metal conductor layer formed over the second insulating layer, vias formed in the second insulating layer connecting the first metal conductor layer to the second metal conductor layer, and a plurality of metal lines. One of the metal lines is expanded around one of the vias compared to metal lines around other ones of the vias so that predetermined areas around each of the vias meets a minimum metal density.

    摘要翻译： 一种半导体器件，包括第一绝缘层，形成在第一绝缘层上的第一金属导体层，包含形成在第一金属导体上的低k绝缘材料的第二绝缘层，形成在第二绝缘层上的第二金属导体层 形成在连接第一金属导体层和第二金属导体层的第二绝缘层中的通孔，以及多个金属线。 与围绕其他通孔的金属线相比，其中一条金属线扩展到其中一条通孔，使得每个通孔周围的预定区域达到最小金属密度。

    METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS
    46.
    发明申请
    METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS 有权
    在金属层之间形成电气连接的方法

    公开(公告)号：US20140038319A1

    公开(公告)日：2014-02-06

    申请号：US13562538

    申请日：2012-07-31

    申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76877 ,  G06F17/5077 ,  H01L21/4763 ,  H01L21/76816 ,  H01L23/5226 ,  H01L29/401 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero.

    摘要翻译： 一种方法包括在第一金属层和第二金属层之间形成连接。 第二金属层在第一金属层之上。 识别用于第一金属层和第二金属层之间的第一通孔的通孔位置。 确定第一个额外通孔的附加位置。 第一个额外的通孔被确定为压力迁移问题所必需的。 确定第二个额外通孔所需的附加位置。 第二个额外的通孔被确定为电迁移问题所必需的。 第一个通路和一个组（i）第一个额外的通孔和第二个额外的通孔（ii）第一个额外的通孔加上一些足够电迁移问题的通孔，考虑到第一个额外的通孔， 考虑到压力迁移问题，仍然有效通过数字大于零。

    Device matching tool and methods thereof
    47.
    发明授权
    Device matching tool and methods thereof 有权
    设备匹配工具及其方法

    公开(公告)号：US08601430B1

    公开(公告)日：2013-12-03

    申请号：US13596337

    申请日：2012-08-28

    申请人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

    发明人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  H01L23/5223 ,  H01L28/88 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method includes identifying at a first instantiation of a device design and a second instantiation of the device design, determining a first value of an electrical performance characteristic of the first instantiation and a second value of the electrical performance characteristic of the second instantiation, determining that the first instantiation matches the second instantiation, wherein the determining is based on the first value, the second value, and a tolerance, and in response to determining that the first and second instantiations do not match, then identifying a first feature of the first instantiation and changing the first feature of the first instantiation.

    摘要翻译： 一种方法包括在设备设计的第一实例和设备设计的第二实例化中识别，确定第一实例的电性能特性的第一值和第二实例的电性能特性的第二值，确定 第一实例化与第二实例化匹配，其中确定基于第一值，第二值和容差，并且响应于确定第一和第二实例不匹配，然后识别第一实例化的第一特征 并改变第一个实例化的第一个特征。

    Methods and apparatus to improve reliability of isolated vias
    48.
    发明授权
    Methods and apparatus to improve reliability of isolated vias 有权
    提高孤立通孔可靠性的方法和装置

    公开(公告)号：US08486839B2

    公开(公告)日：2013-07-16

    申请号：US13114100

    申请日：2011-05-24

    申请人： Douglas M. Reber ,  Lawrence N. Herr

    发明人： Douglas M. Reber ,  Lawrence N. Herr

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76816 ,  G06F17/5081

    摘要： A method for tiling selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and adding tiling features on a metal layer above the selected isolated vias and within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias.

    摘要翻译： 提供了一种在半导体器件中平铺所选择的通孔的方法。 半导体器件包括多个通孔。 该方法包括：生成用于半导体器件的布局数据库; 识别多个通孔中的隔离通孔; 选择隔离通孔; 在每个所选择的隔离通孔周围限定区域; 以及在所选择的隔离通孔上方和区域内的金属层上添加平铺特征。 该方法通过允许湿气从通孔周围排出来提高半导体器件的可靠性。