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    Semiconductor manufacturing using disposable test circuitry within scribe lanes
    1.
    发明授权
    Semiconductor manufacturing using disposable test circuitry within scribe lanes 有权

    公开(公告)号：US10553508B2

    公开(公告)日：2020-02-04

    申请号：US14153417

    申请日：2014-01-13

    申请人： Douglas M. Reber ,  Sergio A. Ajuria ,  Phuc M. Nguyen

    发明人： Douglas M. Reber ,  Sergio A. Ajuria ,  Phuc M. Nguyen

    IPC分类号： H01L21/66 ,  H01L21/78 ,  H01L23/00

    摘要： Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.

    Fuse/resistor utilizing interconnect and vias and method of making
    2.
    发明授权
    Fuse/resistor utilizing interconnect and vias and method of making 有权

    公开(公告)号：US09685405B2

    公开(公告)日：2017-06-20

    申请号：US13907497

    申请日：2013-05-31

    申请人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

    发明人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

    IPC分类号： H01L23/525 ,  H01L23/522 ,  H01L49/02

    CPC分类号： H01L23/5256 ,  H01L23/5228 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure comprising a fuse/resistor structure over a functional layer having a substrate. The fuse/resistor structure includes a via, a first interconnect layer, and a second interconnect layer. The via is over the functional layer and has a first end and a second end vertically opposite the first end, wherein the first end is bounded by a first edge and a second edge opposite the first edge and the second end is bounded by a third edge and a fourth edge opposite the third edge. The first interconnect layer includes a first metal layer running horizontally and contacting the first end and completely extending from the first edge to the second edge. The second interconnect layer includes a second metal layer running horizontally and contacting the second end of the via and extending past the third edge but reaching less than half way to the fourth edge.

    SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFACTURING SAME
    3.
    发明申请
    SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFACTURING SAME 有权
    具有嵌入式电容器的半导体封装及其制造方法

    公开(公告)号：US20160064324A1

    公开(公告)日：2016-03-03

    申请号：US14469645

    申请日：2014-08-27

    申请人： Sergio A. Ajuria ,  Phuc M. Nyugen ,  Douglas M. Reber

    发明人： Sergio A. Ajuria ,  Phuc M. Nyugen ,  Douglas M. Reber

    IPC分类号： H01L23/522 ,  H01L21/283 ,  H01L49/02 ,  H01L21/78

    CPC分类号： H01L28/60 ,  H01L23/3114 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/5223 ,  H01L24/02 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/24137 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.

    摘要翻译： 描述了具有嵌入式电容器的半导体封装和相应的制造方法。 具有嵌入式电容器的半导体封装包括半导体管芯，该半导体管芯具有延伸穿过半导体管芯的第一侧的至少一部分的第一金属层和形成在半导体管芯的第一侧上的封装结构。 嵌入式电容器的第一电导体形成在半导体管芯的第一金属层中。 封装结构包括在其中形成有嵌入式电容器的第二电导体的第二金属层。 嵌入式电容器的电介质位于半导体管芯或半导体封装的封装结构内，以使第一电导体与嵌入式电容器的第二电导体隔离。

    Method and apparatus to improve reliability of vias
    5.
    发明授权
    Method and apparatus to improve reliability of vias 有权
    提高通孔可靠性的方法和装置

    公开(公告)号：US09041209B2

    公开(公告)日：2015-05-26

    申请号：US13299566

    申请日：2011-11-18

    申请人： Douglas M. Reber ,  Lawrence N. Herr

    发明人： Douglas M. Reber ,  Lawrence N. Herr

    IPC分类号： H01L23/498 ,  G06F17/50 ,  H01L21/768

    CPC分类号： G06F17/5068 ,  H01L21/76814 ,  H01L21/76828

    摘要： In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.

    摘要翻译： 在公开的实施例中，在具有多个通孔的半导体器件中平铺所选择的通孔的方法包括生成用于半导体器件的布局数据库; 在多个通孔周围创建区域; 测量每个区域的覆盖金属的密度; 选择低密度区域是具有小于阈值金属密度的金属密度的区域; 并且在低密度区域中的多个通孔上方的金属层上添加至少一个平铺特征，使得低密度区域的金属密度增加至至少与阈值金属密度相同。

    METHOD AND SYSTEM FOR DERIVED LAYER CHECKING FOR SEMICONDUCTOR DEVICE DESIGN
    7.
    发明申请
    METHOD AND SYSTEM FOR DERIVED LAYER CHECKING FOR SEMICONDUCTOR DEVICE DESIGN 有权
    用于半导体器件设计的衍生层检查的方法和系统

    公开(公告)号：US20140040839A1

    公开(公告)日：2014-02-06

    申请号：US13562443

    申请日：2012-07-31

    申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G03F1/00 ,  G06F19/00 ,  G21K5/00

    摘要： A system and method are provided for enabling a systematic detection of issues arising during the course of mask generation for a semiconductor device. IC mask layer descriptions are analyzed and information is generated that identifies devices formed by active layers in the masks, along with a description of all layers in proximity to the found devices. The IC mask information is compared to a netlist file generated from the initial as-designed schematic. Determinations can then made, for example, as to whether all intended devices are present, any conflicting layers are in proximity to or interacting with the intended devices, and any unintended devices are present in the mask layers. Steps can then be taken to resolve the issues presented by the problematic devices.

    摘要翻译： 提供了一种系统和方法，用于能够系统地检测在半导体器件的掩模生成过程中产生的问题。 分析IC掩模层描述，并生成识别掩模中由有源层形成的设备的信息，以及邻近发现的设备的所有层的描述。 将IC掩模信息与从初始设计原理图生成的网表文件进行比较。 然后可以进行例如关于所有预期设备是否存在的确定，任何冲突的层都与预期设备接近或相互作用，并且任何非预期的设备存在于掩模层中。 然后可以采取步骤来解决有问题的设备提出的问题。

    Via placement and electronic circuit design processing method and electronic circuit design utilizing same
    8.
    发明授权
    Via placement and electronic circuit design processing method and electronic circuit design utilizing same 有权
    通过放置和电子电路设计处理方法及利用电子电路设计

    公开(公告)号：US08595667B1

    公开(公告)日：2013-11-26

    申请号：US13661131

    申请日：2012-10-26

    申请人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

    发明人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5072 ,  G06F17/5077

    摘要： A computer-implemented method for processing an electronic circuit design, a method of placing vias within an electronic circuit, and an electronic circuit produced utilizing such method(s) are disclosed. A method embodiment for processing an electronic circuit design comprises accessing, utilizing a computer, data which represents an electronic circuit design, identifying a via metallization feature associated with at least one interconnect metallization feature of the electronic circuit design utilizing data which represents the electronic circuit design. The described method embodiment further comprises evaluating a spacing design rule check on the via metallization feature of the electronic circuit design utilizing an area occupied by the at least one interconnect metallization feature.

    摘要翻译： 公开了一种用于处理电子电路设计的计算机实现的方法，将通孔置于电子电路内的方法以及利用这种方法制造的电子电路。 用于处理电子电路设计的方法实施例包括访问利用计算机的表示电子电路设计的数据，利用代表电子电路设计的数据识别与电子电路设计的至少一个互连金属化特征相关联的通孔金属化特征 。 所描述的方法实施例还包括利用利用至少一个互连金属化特征所占据的面积评估电子电路设计的通孔金属化特征上的间隔设计规则检查。

    SEMICONDUCTOR DEVICE WITH EMBEDDED HEAT SPREADING
    9.
    发明申请
    SEMICONDUCTOR DEVICE WITH EMBEDDED HEAT SPREADING 有权
    具有嵌入式热传播的半导体器件

    公开(公告)号：US20130264700A1

    公开(公告)日：2013-10-10

    申请号：US13442014

    申请日：2012-04-09

    申请人： EDWARD O. TRAVIS ,  Douglas M. Reber ,  Mehul D. Shroff

    发明人： EDWARD O. TRAVIS ,  Douglas M. Reber ,  Mehul D. Shroff

    IPC分类号： H01L23/34 ,  H01L21/768

    CPC分类号： H01L23/373 ,  H01L21/768 ,  H01L23/3677 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a semiconductor substrate and a plurality of clock drivers, wherein the plurality of clock drivers comprises substantially all clock drivers of the semiconductor device, and an interconnect region over the semiconductor substrate, wherein the interconnect region comprises a plurality of heat spreaders, wherein at least 25% of the plurality of clock drivers have a corresponding heat spreader of the plurality of heat spreaders. Each corresponding heat spreader of the plurality of heat spreaders covers at least 50% of a transistor within a corresponding clock driver of the plurality of clock drivers and extends across at least 70% of a perimeter of the transistor within the corresponding clock driver.

    摘要翻译： 半导体器件包括半导体衬底和多个时钟驱动器，其中多个时钟驱动器包括半导体器件的基本上所有的时钟驱动器，以及半导体衬底上的互连区域，其中互连区域包括多个散热器， 其中所述多个时钟驱动器中的至少25％具有所述多个散热器中相应的散热器。 多个散热器的每个相应的散热器覆盖多个时钟驱动器的对应的时钟驱动器内的至少50％的晶体管，并延伸到对应的时钟驱动器内的晶体管的周边的至少70％。