公开(公告)号：US20120052829A1

公开(公告)日：2012-03-01

申请号：US13195563

申请日：2011-08-01

Applicant: In Youl LEE ,  Dae Jin KWON ,  Min Su KIM ,  Chang Hyun KIM ,  Joong Hyun LEE ,  Tae Hoon LEE

Inventor： In Youl LEE ,  Dae Jin KWON ,  Min Su KIM ,  Chang Hyun KIM ,  Joong Hyun LEE ,  Tae Hoon LEE

IPC: H04B17/00

CPC classification number: H04W8/005 ,  H04W48/16 ,  H04W48/18 ,  H04W64/00 ,  H04W72/04

Abstract: A terminal and a network connection method to automatically connect devices to a network and transfer data to the devices using the received signal strength indication (RSSI) levels of signals respectively received from the devices. The terminal may transfer different data to devices based on the RSSI level of the signals received from the devices and/or the locations of the devices.

Abstract translation: 一种终端和网络连接方法，用于使用分别从设备接收的信号的接收信号强度指示（RSSI）电平自动地将设备连接到网络并将数据传送到设备。 终端可以基于从设备接收的信号和/或设备的位置的RSSI级别将不同的数据传送到设备。

公开(公告)号：US07554146B2

公开(公告)日：2009-06-30

申请号：US11317859

申请日：2005-12-23

Applicant: Seok-jun Won ,  Dae-jin Kwon

Inventor： Seok-jun Won ,  Dae-jin Kwon

IPC: H01L29/94

CPC classification number: H01L28/60 ,  H01L21/76895 ,  H01L28/75

Abstract: In a metal-insulator-metal (MIM) capacitor and a method of fabricating the MIM capacitor, a metal-insulator-metal (MIM) capacitor comprises: a lower electrode pattern which is formed on a substrate and includes a conductive layer having a portion as a lower interconnect; a dielectric layer on the lower electrode pattern; a first upper electrode pattern on the dielectric layer; an interlayer insulating layer which covers the first upper electrode pattern, the dielectric layer, and the lower electrode pattern and has a planarized upper surface; a second upper electrode opening pattern formed in the interlayer insulating layer to expose the first upper electrode pattern; a second upper electrode which fills the opening pattern and has an upper surface that is substantially level with an upper surface of the interlayer insulating layer; and an upper interconnect on the interlayer insulating layer and contacts the second upper electrode.

Abstract translation: 在金属绝缘体金属（MIM）电容器和制造MIM电容器的方法中，金属 - 绝缘体 - 金属（MIM）电容器包括：下电极图案，其形成在基板上并且包括具有一部分的导电层 作为下互连; 下电极图案上的电介质层; 电介质层上的第一上电极图案; 覆盖第一上电极图案，电介质层和下电极图案并具有平坦化的上表面的层间绝缘层; 形成在所述层间绝缘层中以暴露所述第一上电极图案的第二上电极开口图案; 填充所述开口图案并具有与所述层间绝缘层的上表面基本平齐的上表面的第二上电极; 以及层间绝缘层上的上互连，并与第二上电极接触。

公开(公告)号：US07435654B2

公开(公告)日：2008-10-14

申请号：US11452828

申请日：2006-06-14

Applicant: Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

Inventor： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC: H01L21/20 ,  H01L21/44

CPC classification number: H01L28/40 ,  H01L21/31637 ,  H01L21/31645

Abstract: There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.

Abstract translation: 提供了具有至少三个高k电介质层的模拟电容器及其制造方法。 模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。 所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。 此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层为 与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。 因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

公开(公告)号：US07297591B2

公开(公告)日：2007-11-20

申请号：US10748308

申请日：2003-12-29

Applicant: Seok-Jun Won ,  Myong-geun Yoon ,  Yong-Kuk Jeong ,  Dae-jin Kwon

Inventor： Seok-Jun Won ,  Myong-geun Yoon ,  Yong-Kuk Jeong ,  Dae-jin Kwon

IPC: H01L21/8242

CPC classification number: H01L21/022 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/56 ,  H01L28/65

Abstract: Provided is a capacitor of a semiconductor device. The capacitor includes a capacitor lower electrode disposed on a semiconductor substrate. A first dielectric layer comprising aluminum oxide (Al2O3) is disposed on the capacitor lower electrode. A second dielectric layer comprising a material having a higher dielectric constant than that of aluminum oxide is disposed on the first dielectric layer. A third dielectric layer comprising aluminum oxide is disposed on the second dielectric layer. A capacitor upper electrode is disposed on the third dielectric layer. The capacitor of the present invention can improve electrical properties. Thus, power consumption can be reduced and capacitance per unit area is high enough to achieve high integration.

Abstract translation: 提供一种半导体器件的电容器。 电容器包括设置在半导体衬底上的电容器下电极。 包含氧化铝（Al 2 O 3 3）的第一电介质层设置在电容器下电极上。 包括具有比氧化铝介电常数更高的介电常数的材料的第二电介质层设置在第一电介质层上。 包含氧化铝的第三电介质层设置在第二电介质层上。 电容器上电极设置在第三电介质层上。 本发明的电容器可以改善电气性能。 因此，可以降低功耗，并且每单位面积的电容足够高以实现高集成度。

公开(公告)号：US07288453B2

公开(公告)日：2007-10-30

申请号：US11063942

申请日：2005-02-23

Applicant: Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon

Inventor： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon

IPC: H01L21/8234

CPC classification number: H01L28/40 ,  H01L21/02183 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/3211

Abstract: There is provided a method of fabricating an analog capacitor using a post-treatment technique. The method includes forming a lower insulating layer on a semiconductor substrate. A bottom electrode is formed on the lower insulating layer, and a capacitor dielectric layer is formed on the bottom electrode. Then, the capacitor dielectric layer is post-treated in a deoxidizing medium. Then, the post-treated capacitor dielectric layer is post-treated in an oxidizing medium. A top electrode is formed on the post-treated capacitor dielectric layer. The analog capacitor fabricated through the post-treatment as above has a low VCC.

Abstract translation: 提供了使用后处理技术制造模拟电容器的方法。 该方法包括在半导体衬底上形成下绝缘层。 底电极形成在下绝缘层上，电容器电介质层形成在底电极上。 然后，将电容器电介质层在脱氧介质中进行后处理。 然后，将后处理电容器电介质层在氧化介质中进行后处理。 顶部电极形成在后处理电容器介电层上。 通过如上所述的后处理制造的模拟电容具有低VCC。

公开(公告)号：US20070026688A1

公开(公告)日：2007-02-01

申请号：US11485523

申请日：2006-07-13

Applicant: Min-Woo Song ,  Seok-Jun Won ,  Weon-Hong Kim ,  Dae-Jin Kwon ,  Jung-Min Park

Inventor： Min-Woo Song ,  Seok-Jun Won ,  Weon-Hong Kim ,  Dae-Jin Kwon ,  Jung-Min Park

IPC: H01L21/20 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/02189 ,  C23C16/405 ,  C23C16/45542 ,  C23C16/45553 ,  C23C16/515 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31641 ,  H01L27/1085 ,  H01L28/40

Abstract: Example embodiments of the present invention relate to a method of forming a dielectric thin film and a method of fabricating a semiconductor memory device having the same. Other example embodiments of the present invention relate to a method of forming a ZrO2 thin film and a method of fabricating a capacitor of a semiconductor memory device using the ZrO2 thin film as a dielectric layer. A method of forming a ZrO2 thin film may include supplying a zirconium precursor on a substrate maintained at a desired temperature, thereby forming a chemisorption layer of the precursor on the substrate. The zirconium precursor may be a tris(N-ethyl-N-methylamino)(tert-butoxy) zirconium precursor. The substrate having the chemisorption layer of the precursor may be exposed to the plasma atmosphere of oxygen-containing gas for a desired time, thereby forming a Zr oxide layer on the substrate, and a method of fabricating a capacitor of a semiconductor memory device having the ZrO2 thin film.

Abstract translation: 本发明的示例性实施例涉及一种形成电介质薄膜的方法及其制造具有该电介质薄膜的半导体存储器件的方法。 本发明的其它示例性实施例涉及形成ZrO 2薄膜的方法和使用ZrO 2薄膜的半导体存储器件的电容器的制造方法 作为电介质层。 形成ZrO 2 H 2薄膜的方法可以包括在保持在所需温度的基板上提供锆前体，由此在基板上形成前体的化学吸附层。 锆前体可以是三（N-乙基-N-甲基氨基）（叔丁氧基）锆前体。 具有前体的化学吸附层的基板可以暴露于含氧气体的等离子体气氛所需的时间，从而在基板上形成Zr氧化物层，以及制造半导体存储器件的电容器的方法，其具有 ZrO 2薄膜。

公开(公告)号：US07166541B2

公开(公告)日：2007-01-23

申请号：US11149498

申请日：2005-06-09

Applicant: Min-Woo Song ,  Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Weon-Hong Kim

Inventor： Min-Woo Song ,  Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC: H01L21/31

CPC classification number: H01L21/02274 ,  C23C16/405 ,  C23C16/45542 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645

Abstract: A method of forming a dielectric layer using a plasma enhanced atomic layer deposition technique includes: loading a semiconductor substrate having a three-dimensional structure into a reaction chamber; and repeatedly performing the following steps until a dielectric layer with a desired thickness is formed: supplying a source gas into the reaction chamber; stopping the supply of the source gas and purging the source gas remaining inside the reaction chamber; and supplying oxygen gas into the reaction chamber after purging the source gas, and applying RF power for oxygen plasma treatment, a level of the applied RF power and a partial pressure of the oxygen gas being increased concurrently with an increased aspect ratio of the three-dimensional structure.

Abstract translation: 使用等离子体增强原子层沉积技术形成电介质层的方法包括：将具有三维结构的半导体衬底加载到反应室中; 并重复执行以下步骤，直到形成具有所需厚度的电介质层：将源气体供应到反应室中; 停止源气体的供给并清除剩余在反应室内的源气体; 并且在净化源气体之后将氧气供应到反应室中，并施加用于氧等离子体处理的RF功率，所施加的RF功率的水平和氧气的分压同时增加， 尺寸结构。

公开(公告)号：US20060234466A1

公开(公告)日：2006-10-19

申请号：US11452828

申请日：2006-06-14

Applicant: Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

Inventor： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC: H01L21/20

CPC classification number: H01L28/40 ,  H01L21/31637 ,  H01L21/31645

Abstract: There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.

Abstract translation: 提供了具有至少三个高k电介质层的模拟电容器及其制造方法。 模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。 所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。 此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层是 与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。 因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

公开(公告)号：US07091548B2

公开(公告)日：2006-08-15

申请号：US10874461

申请日：2004-06-23

Applicant: Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

Inventor： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim

IPC: H01L29/00

CPC classification number: H01L28/40 ,  H01L21/31637 ,  H01L21/31645

Abstract: There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.

Abstract translation: 提供了具有至少三个高k电介质层的模拟电容器及其制造方法。 模拟电容器包括下电极，上电极和介于下电极和上电极之间的至少三个高k电介质层。 所述至少三个高k电介质层包括与下电极接触的底部电介质层，与上电极接触的顶部电介质层和介于底部电介质层和顶部电介质层之间的中间电介质层。 此外，底部电介质层和顶部电介质层中的每一个是高k电介质层，其VCC的二次系数的绝对值与中间介电层的绝对值相对较低，并且中间介电层是 与介电层和顶部电介质层相比，具有低泄漏电流的高k电介质层。 因此，通过使用至少三个高k电介质层，可以优化模拟电容器的VCC特性和漏电流特性。

公开(公告)号：US20060163640A1

公开(公告)日：2006-07-27

申请号：US11339151

申请日：2006-01-25

Applicant: Jung-min Park ,  Seok-jun Won ,  Min-woo Song ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Weon-hong Kim

Inventor： Jung-min Park ,  Seok-jun Won ,  Min-woo Song ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Weon-hong Kim

IPC: H01L29/94

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corresponding to a capacitor cell, on each of the lower electrodes to provide a plurality of MIM capacitor cells constituting one capacitor to which the same electric signal is applied.

Abstract translation: 在制造根据该方法制造的金属 - 绝缘体 - 金属（MIM）电容器和金属 - 绝缘体 - 金属（MIM））电容器的方法中，所述方法包括：在半导体衬底上形成绝缘层图案， 层图案具有分别限定要形成电容器单元的区域的多个开口; 在绝缘层图案和半导体衬底上形成下电极导电层; 形成填充所述下电极导电层上的开口的第一牺牲层; 在所述第一牺牲层上形成第二牺牲层; 平面化第二牺牲层; 暴露下电极导电层的上表面; 去除暴露的下电极导电层以形成彼此分离的多个下电极，每个相应于电容器单元; 并且在每个下电极上形成各自对应于电容器单元的电介质层和上电极，以提供构成相同电信号的一个电容器的多个MIM电容器单元。