Formation of a high-K crystalline dielectric composition
    41.
    发明授权
    Formation of a high-K crystalline dielectric composition 有权
    形成高K结晶介电组合物

    公开(公告)号:US08476155B1

    公开(公告)日:2013-07-02

    申请号:US12835790

    申请日:2010-07-14

    Abstract: Provided are a method of forming a dielectric and a method of fabricating a semiconductor device. The method includes forming a preliminary dielectric including Hf, O and an “A” element on an underlying layer. The preliminary dielectric is formed in an amorphous structure or a mixed structure of an amorphous structure and an “M” crystalline structure. The “A” element about 1 at % to about 5 at % of the total content of the “A” element and Hf in the preliminary dielectric. Through a nitridation process, nitrogen is added to the preliminary dielectric. The nitrogen-containing dielectric is changed into a dielectric having a “T” crystalline structure through a phase transition process, wherein the “T” crystalline structure is different from the “M” crystalline structure. An upper layer is formed on the “T” crystalline dielectric.

    Abstract translation: 提供形成电介质的方法和制造半导体器件的方法。 该方法包括在下层上形成包含Hf,O和“A”元素的预备电介质。 预置电介质形成为非晶结构或非晶结构和“M”晶体结构的混合结构。 “A”元素在“A”元素的总含量和预置电介质中的Hf的约1at%至约5at%的“A”元素。 通过氮化处理,将氮气加入到初步电介质中。 通过相变过程将含氮电介质变成具有“T”晶体结构的电介质,其中“T”晶体结构不同于“M”晶体结构。 在“T”晶体电介质上形成上层。

    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    42.
    发明申请
    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
    制造半导体器件的方法

    公开(公告)号:US20120309145A1

    公开(公告)日:2012-12-06

    申请号:US13417787

    申请日:2012-03-12

    CPC classification number: H01L21/823412 H01L21/823807

    Abstract: Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas.

    Abstract translation: 制造半导体器件的方法包括提供包括NMOS区域和PMOS区域的衬底,将氟离子注入到衬底的上表面中,形成NMOS区域的第一栅极电极和衬底上的PMOS区域的第二栅极电极 在所述基板的与所述第一栅电极和所述第二栅电极的两个侧面相邻的部分分别形成源极区域和漏极区域,并在所述第一栅极电极和所述第二栅极电极的上表面上进行高压热处理工序 通过使用非氧化气体的基板。

    Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors
    45.
    发明申请
    Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors 有权
    具有多层介质膜的晶体管及其制造方法

    公开(公告)号:US20100025781A1

    公开(公告)日:2010-02-04

    申请号:US12574912

    申请日:2009-10-07

    Abstract: Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

    Abstract translation: 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜,该电介质膜的厚度至少为多层电介质膜的厚度的50%,并且包括金属氧化物,金属硅酸盐,铝酸盐或其混合物,以及上电介质膜 在下介电膜上,上电介质膜包含III族金属氧化物,III族金属氮化物,第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。

    Transistors with multilayered dielectric films
    46.
    发明授权
    Transistors with multilayered dielectric films 有权
    具有多层介电膜的晶体管

    公开(公告)号:US07615830B2

    公开(公告)日:2009-11-10

    申请号:US11252514

    申请日:2005-10-18

    Abstract: Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

    Abstract translation: 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜,该电介质膜的厚度至少为多层电介质膜的厚度的50%,并且包括金属氧化物,金属硅酸盐,铝酸盐或其混合物,以及上电介质膜 在下介电膜上,上电介质膜包含III族金属氧化物,III族金属氮化物,第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。

    Semiconductor devices having nitrogen-incorporated active region and methods of fabricating the same
    47.
    发明授权
    Semiconductor devices having nitrogen-incorporated active region and methods of fabricating the same 有权
    具有氮结合有源区的半导体器件及其制造方法

    公开(公告)号:US07547951B2

    公开(公告)日:2009-06-16

    申请号:US11396702

    申请日:2006-04-04

    CPC classification number: H01L21/823807 H01L21/823857

    Abstract: A semiconductor device may include a semiconductor substrate having a first region and a second region. The nitrogen-incorporated active region may be formed within the first region. A first gate electrode may be formed on the nitrogen-incorporated active region. A first gate dielectric layer may be interposed between the nitrogen-incorporated active region and the first gate electrode. The first gate dielectric layer may include a first dielectric layer and a second dielectric layer. The second dielectric layer may be a nitrogen contained dielectric layer. A second gate electrode may be formed on the second region. A second gate dielectric layer may be interposed between the second region and the second gate electrode. The first gate dielectric layer may have the same or substantially the same thickness as the second gate dielectric layer, and the nitrogen contained dielectric layer may contact with the nitrogen-incorporated active region.

    Abstract translation: 半导体器件可以包括具有第一区域和第二区域的半导体衬底。 可以在第一区域内形成含氮的有源区。 可以在引入氮的有源区上形成第一栅电极。 第一栅极电介质层可插入在引入氮的有源区和第一栅电极之间。 第一栅介质层可以包括第一介电层和第二介电层。 第二电介质层可以是含氮介电层。 第二栅极电极可以形成在第二区域上。 可以在第二区域和第二栅电极之间插入第二栅极电介质层。 第一栅极介电层可以具有与第二栅极介电层相同或基本相同的厚度,并且含氮介电层可以与引入氮的有源区接触。

    Transistors with multilayered dielectric films and methods of manufacturing such transistors
    49.
    发明申请
    Transistors with multilayered dielectric films and methods of manufacturing such transistors 有权
    具有多层介电膜的晶体管和制造这种晶体管的方法

    公开(公告)号:US20060081948A1

    公开(公告)日:2006-04-20

    申请号:US11252514

    申请日:2005-10-18

    Abstract: Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

    Abstract translation: 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜,该电介质膜的厚度至少为多层电介质膜的厚度的50%,并且包括金属氧化物,金属硅酸盐,铝酸盐或其混合物,以及上电介质膜 在下介电膜上,上电介质膜包含III族金属氧化物,III族金属氮化物,第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。

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