公开(公告)号：US07190000B2

公开(公告)日：2007-03-13

申请号：US10915958

申请日：2004-08-11

申请人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

发明人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

IPC分类号： H01L29/04

CPC分类号： G02F1/136227 ,  G02F2001/136236 ,  H01L27/1244 ,  H01L27/1248

摘要： A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：顺序地形成在基板上的栅极线，栅极绝缘层和半导体层; 至少形成在所述半导体层上的数据线和漏电极; 形成在所述数据线和所述漏电极上的第一钝化层，并且具有至少部分地暴露所述漏电极的第一接触孔; 第二钝化层，其形成在所述第一钝化层上，并且具有设置在所述第一接触孔上并具有放置在所述第一接触孔外部的第一底部边缘的第二接触孔和放置在所述第一接触孔内部的第二底部边缘; 以及形成在所述第二钝化层上并通过所述第一和第二接触孔连接到所述漏电极的像素电极。

公开(公告)号：US08772897B2

公开(公告)日：2014-07-08

申请号：US13049783

申请日：2011-03-16

申请人： Ki-Won Kim ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

发明人： Ki-Won Kim ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

IPC分类号： H01L27/146

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/78645 ,  H01L29/78648

摘要： A thin-film transistor includes a semiconductor pattern, a first gate electrode, a source electrode, a drain electrode and a second gate electrode. The semiconductor pattern is formed on a substrate. A first conductive layer has a pattern that includes the first gate electrode which is electrically insulated from the semiconductor pattern. A second conductive layer has a pattern that includes a source electrode electrically connected to the semiconductor pattern, a drain electrode spaced apart from the source electrode, and a second gate electrode electrically connected to the first gate electrode. The second gate electrode is electrically insulated from the semiconductor pattern, the source electrode and the drain electrode.

摘要翻译： 薄膜晶体管包括半导体图案，第一栅电极，源电极，漏电极和第二栅电极。 半导体图案形成在基板上。 第一导电层具有包括与半导体图案电绝缘的第一栅电极的图案。 第二导电层具有图案，其包括电连接到半导体图案的源电极，与源电极间隔开的漏电极和与第一栅电极电连接的第二栅电极。 第二栅电极与半导体图案，源电极和漏电极电绝缘。

公开(公告)号：US08723179B2

公开(公告)日：2014-05-13

申请号：US12957743

申请日：2010-12-01

申请人： Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

发明人： Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

摘要： A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

摘要翻译： 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US08598583B2

公开(公告)日：2013-12-03

申请号：US13092882

申请日：2011-04-22

申请人： Hye-Young Ryu ,  Jin-Won Lee ,  Woo-Geun Lee ,  Hee-Jun Byeon ,  Xun Zhu

发明人： Hye-Young Ryu ,  Jin-Won Lee ,  Woo-Geun Lee ,  Hee-Jun Byeon ,  Xun Zhu

IPC分类号： H01L29/786

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/3272 ,  H01L51/5253 ,  H01L2227/323

摘要： A thin film transistor panel includes a substrate, a light blocking layer on the substrate, a first protective film on the light blocking layer, a first electrode and a second electrode on the first protective film, an oxide semiconductor layer on a portion of the first protective film exposed between the first electrode and the second electrode, an insulating layer, a third electrode overlapping with the oxide semiconductor layer and on the insulating layer, and a fourth electrode on the insulating layer. The light blocking layer includes first sidewalls, and the first protective film includes second sidewalls. The first and the second sidewalls are disposed along substantially the same line.

公开(公告)号：US20120037911A1

公开(公告)日：2012-02-16

申请号：US13205132

申请日：2011-08-08

申请人： Ki-Won Kim ,  Kyoung-Jae Chung ,  Hye-Young Ryu ,  Young-Joo Choi ,  Seung-Ha Choi ,  Kap-Soo Yoon

发明人： Ki-Won Kim ,  Kyoung-Jae Chung ,  Hye-Young Ryu ,  Young-Joo Choi ,  Seung-Ha Choi ,  Kap-Soo Yoon

IPC分类号： H01L29/786 ,  H01L33/08

CPC分类号： H01L27/1225 ,  H01L29/66969 ,  H01L29/7869

摘要： A display substrate includes a gate wire formed on an insulating substrate, a semiconductor pattern formed on the gate wire and containing a metal oxynitride compound, and a data wire formed on the semiconductor pattern to cross the gate wire. The semiconductor pattern has a carrier number density ranging from 1016/cm3 to 1019/cm3.

摘要翻译： 显示基板包括形成在绝缘基板上的栅极线，形成在栅极线上并含有金属氮氧化合物的半导体图案，以及形成在半导体图案上以跨过栅极线的数据线。 半导体图案的载体数密度范围为1016 / cm3至1019 / cm3。

公开(公告)号：US20120037906A1

公开(公告)日：2012-02-16

申请号：US13115088

申请日：2011-05-24

申请人： Hye-Young RYU ,  Woo-Geun LEE ,  Young-Joo CHOI ,  Kyoung-Jae CHUNG ,  Jin-Won LEE ,  Seung-Ha CHOI ,  Hee-Jun BYEON ,  Pil-Sang YUN

发明人： Hye-Young RYU ,  Woo-Geun LEE ,  Young-Joo CHOI ,  Kyoung-Jae CHUNG ,  Jin-Won LEE ,  Seung-Ha CHOI ,  Hee-Jun BYEON ,  Pil-Sang YUN

IPC分类号： H01L29/786 ,  H01L21/44

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/1255

摘要： A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.

摘要翻译： 提供了能够降低由于氧化物半导体图案的劣化引起的器件劣化的薄膜晶体管阵列基板及其制造方法。 薄膜晶体管阵列基板可以包括其上形成有栅极的绝缘基板，形成在绝缘基板上的栅极绝缘膜，设置在栅极绝缘膜上的氧化物半导体图案，形成在氧化物半导体上的抗蚀刻图案 图案，以及形成在防蚀刻图案上的源电极和漏电极。 氧化物半导体图案可以包括位于源电极和漏电极之间的边缘部分，并且边缘部分可以包括至少一个导电区域和至少一个非导电区域。

公开(公告)号：US07977677B2

公开(公告)日：2011-07-12

申请号：US11840161

申请日：2007-08-16

申请人： Hye-Young Ryu ,  Jang-Soo Kim ,  Su-Hyoung Kang

发明人： Hye-Young Ryu ,  Jang-Soo Kim ,  Su-Hyoung Kang

IPC分类号： H01L29/04

CPC分类号： G02F1/136227 ,  G02F2001/136222 ,  H01L27/3258

摘要： In a thin-film transistor (TFT) substrate, a gate insulating layer is disposed on a gate electrode electrically connected to a gate line. A semiconductor layer is disposed on the gate insulating layer. A source electrode is electrically connected to a data line that intersects the gate line. A drain electrode faces the source electrode and defines a channel area of a semiconductor layer. An organic layer is disposed on the data line and has a first opening exposing the channel area. An inorganic insulating layer is disposed on the organic layer. A pixel electrode is disposed on the inorganic insulating layer and electrically connected to the drain electrode. The inorganic insulating layer covers the first opening, and thickness of the inorganic insulating layer is substantially uniform.

摘要翻译： 在薄膜晶体管（TFT）基板中，栅极绝缘层设置在与栅极线电连接的栅电极上。 半导体层设置在栅极绝缘层上。 源极电极与与栅极线相交的数据线电连接。 漏电极面对源电极并限定半导体层的沟道面积。 有机层设置在数据线上，并且具有暴露通道区域的第一开口。 无机绝缘层设置在有机层上。 像素电极设置在无机绝缘层上并与漏电极电连接。 无机绝缘层覆盖第一开口，无机绝缘层的厚度基本均匀。

公开(公告)号：US07888675B2

公开(公告)日：2011-02-15

申请号：US12099718

申请日：2008-04-08

申请人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

发明人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC分类号： H01L21/00

CPC分类号： H01L27/124 ,  G02F2001/13629 ,  H01L29/458

摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

摘要翻译： 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US20090141227A1

公开(公告)日：2009-06-04

申请号：US12101079

申请日：2008-04-10

申请人： Hye-Young RYU

发明人： Hye-Young RYU

IPC分类号： G02F1/133 ,  G02F1/1343

CPC分类号： G02F1/1333 ,  G02F2001/133354 ,  G02F2001/133388 ,  G02F2001/136222 ,  G02F2001/136231

摘要： A display substrate includes a transparent insulating substrate, a transparent common electrode, a dummy pattern and a key pattern. The transparent insulating substrate has a display area and a non-display area. Images are displayed in the display area, and the non-display area surrounds the display area. The transparent common electrode is formed in the display area of the insulating substrate. The dummy pattern is formed in the non-display area of the insulating substrate. The dummy pattern is formed from the same material as the common electrode. The key pattern is formed on the dummy pattern. The key pattern may include a metal or an opaque photoresist. Therefore, a process of manufacturing the display substrate may be simplified.

摘要翻译： 显示基板包括透明绝缘基板，透明公共电极，虚设图案和键图案。 透明绝缘基板具有显示区域和非显示区域。 图像显示在显示区域中，非显示区域围绕显示区域。 透明公共电极形成在绝缘基板的显示区域中。 虚设图案形成在绝缘基板的非显示区域中。 虚设图案由与公共电极相同的材料形成。 键图案形成在虚拟图案上。 键图案可以包括金属或不透明光致抗蚀剂。 因此，可以简化显示基板的制造工艺。

公开(公告)号：US20080299712A1

公开(公告)日：2008-12-04

申请号：US12192531

申请日：2008-08-15

申请人： Woo-Geun LEE ,  Hye-Young RYU ,  Sang-Gab KIM ,  Jang-Soo KIM

发明人： Woo-Geun LEE ,  Hye-Young RYU ,  Sang-Gab KIM ,  Jang-Soo KIM

IPC分类号： H01L21/336

CPC分类号： H01L27/1288 ,  H01L21/32134 ,  H01L21/76838 ,  H01L27/1214 ,  H01L29/66765

摘要： A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode, forming a gate insulating layer on the gate line, forming a semiconductor stripe on the gate insulating layer; forming ohmic contacts on the semiconductor stripe, forming a data line including a source electrode and a drain electrode on the ohmic contacts, depositing a passivation layer on the data line and the drain electrode, and forming a pixel electrode connected to the drain electrode. The formation of the data line and the drain electrode, the ohmic contacts, and the semiconductor stripe includes depositing an intrinsic silicon layer, an extrinsic silicon layer, and a conductor layer on the gate insulating layer, forming a photoresist including a second portion corresponding to a channel area between the source electrode and the drain electrode, and a first portion corresponding to a wire area on the data line and the drain electrode, wherein the first portion is thicker than the second portion, etching the conductor layer corresponding to a remaining area except for the wire and the channel area using the photoresist as an etch mask, removing the second portion to expose the conductor layer on the channel areas, etching the intrinsic silicon layer and the extrinsic silicon layer on the remaining area, etching the conductor layer and the extrinsic silicon layer on the channel areas, and removing the first portion.

摘要翻译： 制造薄膜晶体管阵列面板的方法包括：形成包括栅电极的栅极线，在栅极线上形成栅绝缘层，在栅绝缘层上形成半导体条; 在半导体条上形成欧姆接触，在欧姆接触上形成包括源电极和漏电极的数据线，在数据线和漏电极上沉积钝化层，并形成连接到漏电极的像素电极。 数据线和漏电极，欧姆接触和半导体条纹的形成包括在栅绝缘层上沉积本征硅层，非本征硅层和导体层，形成光致抗蚀剂，其包括对应于 源极电极和漏极电极之间的沟道区域，以及对应于数据线和漏极电极的导线区域的第一部分，其中第一部分比第二部分厚，蚀刻对应于剩余区域的导体层 除了使用光致抗蚀剂作为蚀刻掩模的导线和沟道区域之外，去除第二部分以暴露沟道区域上的导体层，蚀刻剩余区域上的本征硅层和非本征硅层，蚀刻导体层和 在通道区域上的非本征硅层，以及去除第一部分。