公开(公告)号：US08359501B1

公开(公告)日：2013-01-22

申请号：US13183253

申请日：2011-07-14

Applicant: Hyun Lee ,  Jayesh R. Bhakta ,  Soonju Choi

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Soonju Choi

IPC: G11C29/00

CPC classification number: G11C29/12 ,  G11C5/04

Abstract: A self-testing memory module includes a printed circuit board configured to be operatively coupled to a memory controller of a computer system and includes a plurality of memory devices on the printed circuit board, each memory device of the plurality of memory devices comprising data, address, and control ports. The memory module also includes a control module configured to generate address and control signals for testing the memory devices. The memory module includes a data module comprising a plurality of data handlers. Each data handler is operable independently from each of the other data handlers of the plurality of data handlers. Each data handler is operatively coupled to a corresponding plurality of the data ports of one or more of the memory devices and is configured to generate data for writing to the corresponding plurality of data ports.

Abstract translation: 自检存储器模块包括被配置为可操作地耦合到计算机系统的存储器控​​制器的印刷电路板，并且在印刷电路板上包括多个存储器件，多个存储器件中的每个存储器件包括数据，地址 和控制端口。 存储器模块还包括被配置为产生用于测试存储器件的地址和控制信号的控制模块。 存储器模块包括包括多个数据处理器的数据模块。 每个数据处理程序可独立于多个数据处理程序中的每个其他数据处理程序操作。 每个数据处理器可操作地耦合到一个或多个存储器件的对应的多个数据端口，并且被配置为产生用于写入对应的多个数据端口的数据。

公开(公告)号：US08287291B1

公开(公告)日：2012-10-16

申请号：US13231870

申请日：2011-09-13

Applicant: Jayesh R. Bhakta ,  Enchao Yu ,  Chi She Chen ,  Richard E. Flaig

Inventor： Jayesh R. Bhakta ,  Enchao Yu ,  Chi She Chen ,  Richard E. Flaig

IPC: H01R12/00

CPC classification number: H05K1/147 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/141 ,  H05K3/4691 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2203/1572 ,  H01L2224/0401

Abstract: A circuit includes a first plurality of contacts configured to be in electrical communication with a plurality of electronic devices. The circuit card further includes a flexible portion including a dielectric layer, a second plurality of contacts, and a plurality of electrical conduits extending across a region of the flexible portion and in electrical communication with one or more contacts of the first plurality of contacts and with the second plurality of contacts. The flexible portion further includes an electrically conductive layer extending across the region of the flexible portion. The electrically conductive layer is superposed with the plurality of electrical conduits with the dielectric layer therebetween. The electrically conductive layer does not overlay one or more portions of the dielectric layer in the region of the flexible portion.

Abstract translation: 电路包括构造成与多个电子设备电通信的第一多个触点。 电路卡还包括柔性部分，该柔性部分包括电介质层，第二多个触点以及跨越柔性部分的区域延伸并且与第一多个触点的一个或多个触点电连通并且与 第二个多个联系人。 柔性部分还包括延伸穿过柔性部分的区域的导电层。 导电层与多个电导管重叠，其间具有介电层。 在柔性部分的区域中，导电层不覆盖电介质层的一个或多个部分。

公开(公告)号：US08081536B1

公开(公告)日：2011-12-20

申请号：US13032470

申请日：2011-02-22

Applicant: Jeffrey C. Solomon ,  Jayesh R. Bhakta

Inventor： Jeffrey C. Solomon ,  Jayesh R. Bhakta

IPC: G11C8/00

CPC classification number: G06F13/1673 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4243 ,  G06F13/4282 ,  G11C5/04 ,  G11C7/1072 ,  G11C15/00

Abstract: A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory circuits activated by a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals smaller than the first number of chip-select signals. The circuit is further configurable to generate phase-locked clock signals, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response at least in part to the set of signals, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.

Abstract translation: 电路被配置为安装在被配置为可操作地耦合到计算机系统的存储器模块上。 存储器模块具有由第一数量的芯片选择信号激活的第一数量的双数据速率（DDR）存储器电路。 电路可配置为接收包括地址信号和小于第一数量的芯片选择信号的第二数量的芯片选择信号的信号。 该电路还可配置成产生锁相时钟信号，以至少部分地响应于该组信号来选择性地隔离来自计算机系统的第一数量级别的至少一级的负载，并且产生第一 芯片选择信号的数量至少部分地响应于锁相时钟信号，地址信号和第二数量的芯片选择信号。

公开(公告)号：US08001434B1

公开(公告)日：2011-08-16

申请号：US12422925

申请日：2009-04-13

Applicant: Hyun Lee ,  Jayesh R. Bhakta ,  Soonju Choi

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Soonju Choi

IPC: G01R31/28 ,  G11C29/00

CPC classification number: G11C29/12 ,  G11C5/04

Abstract: A self-testing memory module includes a printed circuit board configured to be operatively coupled to a memory controller of a computer system and includes a plurality of memory devices on the printed circuit board, each memory device of the plurality of memory devices comprising data, address, and control ports. The memory module also includes a control module configured to generate address and control signals for testing the memory devices. The memory module includes a data module comprising a plurality of data handlers. Each data handler is operable independently from each of the other data handlers of the plurality of data handlers. Each data handler is operatively coupled to a corresponding plurality of the data ports of one or more of the memory devices and is configured to generate data for writing to the corresponding plurality of data ports.

Abstract translation: 自检存储器模块包括被配置为可操作地耦合到计算机系统的存储器控​​制器的印刷电路板，并且在印刷电路板上包括多个存储器件，多个存储器件中的每个存储器件包括数据，地址 和控制端口。 存储器模块还包括被配置为产生用于测试存储器件的地址和控制信号的控制模块。 存储器模块包括包括多个数据处理器的数据模块。 每个数据处理程序可独立于多个数据处理程序中的每个其他数据处理程序操作。 每个数据处理器可操作地耦合到一个或多个存储器件的对应的多个数据端口，并且被配置为产生用于写入对应的多个数据端口的数据。

公开(公告)号：US07619912B2

公开(公告)日：2009-11-17

申请号：US11862931

申请日：2007-09-27

Applicant: Jayesh R. Bhakta ,  Jeffrey C. Solomon

Inventor： Jayesh R. Bhakta ,  Jeffrey C. Solomon

IPC: G11C15/02

CPC classification number: G11C8/12 ,  G06F12/0207 ,  G06F12/0215 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1048 ,  G11C2207/105 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611

Abstract: A memory module connectable to a computer system includes a printed circuit board, a plurality of memory devices coupled to the printed circuit board, and a logic element coupled to the printed circuit board. The plurality of memory devices has a first number of memory devices. The logic element receives a set of input control signals from the computer system. The set of input control signals corresponds to a second number of memory devices smaller than the first number of memory devices. The logic element generates a set of output control signals in response to the set of input control signals. The set of output control signals corresponds to the first number of memory devices.

Abstract translation: 可连接到计算机系统的存储器模块包括印刷电路板，耦合到印刷电路板的多个存储器件以及耦合到印刷电路板的逻辑元件。 多个存储器件具有第一数量的存储器件。 逻辑元件从计算机系统接收一组输入控制信号。 该组输入控制信号对应于小于第一数量的存储器件的第二数量的存储器件。 逻辑元件响应于该组输入控制信号产生一组输出控制信号。 该组输出控制信号对应于第一数量的存储器件。

公开(公告)号：US07442050B1

公开(公告)日：2008-10-28

申请号：US11511523

申请日：2006-08-28

Applicant: Jayesh R. Bhakta ,  Enchao Yu ,  Chi She Chen ,  Richard E. Flaig

Inventor： Jayesh R. Bhakta ,  Enchao Yu ,  Chi She Chen ,  Richard E. Flaig

IPC: H01R12/00

CPC classification number: H05K1/147 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/141 ,  H05K3/4691 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2203/1572 ,  H01L2224/0401

Abstract: A circuit card includes a rigid portion having a first plurality of contacts configured to be in electrical communication with a plurality of memory devices. The circuit card further includes a flexible connector coupled to the rigid portion. The flexible connector has a first side and a second side. The flexible connector comprises a dielectric layer, a second plurality of contacts configured to be in electrical communication with a substrate, and a plurality of electrical conduits on the first side of the flexible connector and extending from the rigid portion to the second plurality of contacts. The plurality of electrical conduits is in electrical communication with one or more contacts of the first plurality of contacts and with the second plurality of contacts. The flexible connector further includes an electrically conductive layer on the second side of the flexible connector. The electrically conductive layer is superposed with the plurality of electrical conduits with the dielectric layer therebetween. The electrically conductive layer does not cover one or more portions of the second side of the flexible connector, thereby providing improved flexibility of the flexible connector.

Abstract translation: 电路卡包括具有构造成与多个存储器件电连通的第一多个触点的刚性部分。 电路卡还包括耦合到刚性部分的柔性连接器。 柔性连接器具有第一侧和第二侧。 柔性连接器包括电介质层，构造成与衬底电连通的第二多个触点，以及在柔性连接器的第一侧上并从刚性部分延伸到第二多个触点的多个电导体。 多个电导管与第一组多个触头中的一个或多个触头和第二组触头电连接。 柔性连接器还包括在柔性连接器的第二侧上的导电层。 导电层与多个电导管重叠，其间具有介电层。 导电层不覆盖柔性连接器的第二侧的一个或多个部分，从而提供柔性连接器的改进的柔性。

公开(公告)号：US07286436B2

公开(公告)日：2007-10-23

申请号：US11075395

申请日：2005-03-07

Applicant: Jayesh R. Bhakta ,  Jeffrey Solomon ,  William M. Gervasi

Inventor： Jayesh R. Bhakta ,  Jeffrey Solomon ,  William M. Gervasi

IPC: G11C8/00

CPC classification number: G11C5/066 ,  G11C5/04 ,  G11C7/1048 ,  G11C2207/105

Abstract: A memory module comprises a plurality of memory components. Each memory component has a first bit width. The plurality of memory components are configured as one or more pairs of memory components. Each pair of memory components simulates a single virtual memory component having a second bit width which is twice the first bit width.

Abstract translation: 存储器模块包括多个存储器组件。 每个存储器组件具有第一位宽度。 多个存储器组件被配置为一对或多对存储器组件。 每对存储器组件模拟具有第二位宽度的第二位宽度的两倍的单个虚拟存储器组件。

公开(公告)号：US07254036B2

公开(公告)日：2007-08-07

申请号：US11101155

申请日：2005-04-07

Applicant: Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

Inventor： Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

IPC: H05K7/20

CPC classification number: H05K1/0203 ,  H05K1/144 ,  H05K2201/10189 ,  H05K2201/1056 ,  H05K2201/2018 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/4913

Abstract: A module is electrically connectable to a computer system. The module includes a frame having an edge connector with a plurality of electrical contacts which are electrically connectable to the computer system. The module further includes a first printed circuit board coupled to the frame. The first printed circuit board has a first surface and a first plurality of components mounted on the first surface. The first plurality of components is electrically coupled to the electrical contacts of the edge connector. The module further includes a second printed circuit board coupled to the frame. The second printed circuit board has a second surface and a second plurality of components mounted on the second surface. The second plurality of components is electrically coupled to the electrical contacts of the edge connector. The second surface of the second printed circuit board faces the first surface of the first printed circuit board. The module further includes at least one thermally conductive layer positioned between the first plurality of components and the second plurality of components. The at least one thermally conductive layer is thermally coupled to the first plurality of components, to the second plurality of components, and to the electrical contacts of the edge connector.

Abstract translation: 模块可电连接到计算机系统。 该模块包括具有边缘连接器的框架，该边缘连接器具有可与计算机系统电连接的多个电触点。 模块还包括耦合到框架的第一印刷电路板。 第一印刷电路板具有安装在第一表面上的第一表面和第一多个部件。 第一多个部件电耦合到边缘连接器的电触头。 模块还包括耦合到框架的第二印刷电路板。 第二印刷电路板具有安装在第二表面上的第二表面和第二多个部件。 第二多个部件电耦合到边缘连接器的电触头。 第二印刷电路板的第二表面面向第一印刷电路板的第一表面。 模块还包括位于第一多个部件和第二多个部件之间的至少一个导热层。 所述至少一个导热层热耦合到所述第一多个部件，所述第二多个部件以及所述边缘连接器的所述电触头。

公开(公告)号：US06930903B2

公开(公告)日：2005-08-16

申请号：US10765488

申请日：2004-01-27

Applicant: Jayesh R. Bhakta ,  Robert S. Pauley, Jr.

Inventor： Jayesh R. Bhakta ,  Robert S. Pauley, Jr.

IPC: G11C5/00 ,  H05K1/02 ,  H05K1/18 ,  G11C5/06 ,  G06F12/00 ,  G06F13/00 ,  G11C5/02 ,  G11C19/00

CPC classification number: H05K1/181 ,  H05K1/0266 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10689 ,  Y02P70/611

Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

Abstract translation: 使用标准商业包装的集成电路布置在印刷电路板上，以允许生产1千兆字节和2千兆字节容量的存储器模块。 第一排集成电路定向成与第二排集成电路相反的方向。 第一行的前半部分和第二行的相应一半中的集成电路经由信号线连接到第一寄存器。 第一行的后半部分和第二行的相应一半中的集成电路连接到第二寄存器。 每个寄存器处理每个数据字中位的不连续子集。