公开(公告)号：US20090032841A1

公开(公告)日：2009-02-05

申请号：US11832449

申请日：2007-08-01

Applicant: Manfred Eller ,  Jin-Ping Han

Inventor： Manfred Eller ,  Jin-Ping Han

IPC: H01L29/778 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.

Abstract translation: 公开了半导体器件及其制造方法。 在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片上形成栅极电介质，并在栅极电介质上形成栅极。 至少一个凹部形成在靠近栅极和栅极电介质的半导体晶片中，至少一个凹部的至少一部分在栅极下方延伸。 半导体晶片中的至少一个凹部填充有半导体材料。

公开(公告)号：US20080119025A1

公开(公告)日：2008-05-22

申请号：US11603276

申请日：2006-11-21

Applicant: O Sung Kwon ,  Oh Jung Kwon ,  Jin-Ping Han ,  Henry Utomo

Inventor： O Sung Kwon ,  Oh Jung Kwon ,  Jin-Ping Han ,  Henry Utomo

IPC: H01L21/336 ,  H01L21/20

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: In a method of making a semiconductor device, a recess is formed in an upper surface of the semiconductor body of a first material. An embedded semiconductor region is formed in the recess. The embedded semiconductor region is formed from a second semiconductor material that is different than the first semiconductor material. An upper surface of the embedded semiconductor region is amorphized to create an amorphous region. A silicide is then formed over the amorphous region.

Abstract translation: 在制造半导体器件的方法中，在第一材料的半导体本体的上表面中形成凹部。 嵌入式半导体区域形成在凹部中。 嵌入式半导体区域由与第一半导体材料不同的第二半导体材料形成。 嵌入式半导体区域的上表面非晶化以产生非晶区域。 然后在无定形区域上形成硅化物。

公开(公告)号：US20080076214A1

公开(公告)日：2008-03-27

申请号：US11526499

申请日：2006-09-25

Applicant: Jin-Ping Han ,  Haoren Zhuang ,  Jiang Yan ,  Jingyu Lian ,  Manfred Eller

Inventor： Jin-Ping Han ,  Haoren Zhuang ,  Jiang Yan ,  Jingyu Lian ,  Manfred Eller

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L29/4983 ,  H01L21/28017 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/82385 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

Abstract: A method of making a semiconductor device is disclosed. A device is fabricated on a semiconductor body. A gate electrode is disposed over the semiconductor body with a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric has a length greater than the gate electrode. A first source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the first source/drain region, and a second source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the second source/drain region.

Abstract translation: 公开了制造半导体器件的方法。 器件制造在半导体主体上。 栅电极设置在半导体本体上，在栅电极和半导体本体之间具有栅极电介质，其中栅极电介质具有大于栅电极的长度。 第一源极/漏极区域设置在与栅极的第一边缘相邻的半导体本体内，栅极电介质至少部分地与第一源极/漏极区域重叠，并且第二源极/漏极区域设置在与半导体本体相邻的第二源极/漏极区域内 具有栅极电介质的栅极的第一边缘至少部分地与第二源极/漏极区重叠。

公开(公告)号：US20070295989A1

公开(公告)日：2007-12-27

申请号：US11473883

申请日：2006-06-23

Applicant: Jin-Ping Han ,  Hung Y. Ng ,  Judson R. Holt

Inventor： Jin-Ping Han ,  Hung Y. Ng ,  Judson R. Holt

IPC: H01L31/00 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor body is formed from a first semiconductor material, e.g., silicon. A compound semiconductor region, e.g., silicon germanium, is embedded in the semiconductor body. The compound semiconductor region includes the first semiconductor material and a second semiconductor material. The compound semiconductor region has a concentration of the second semiconductor material that varies along an interface between the side portion of the compound semiconductor region and the side portion of the semiconductor body

Abstract translation: 半导体本体由诸如硅的第一半导体材料形成。 诸如硅锗的化合物半导体区域被嵌入在半导体本体中。 化合物半导体区域包括第一半导体材料和第二半导体材料。 化合物半导体区域具有沿着化合物半导体区域的侧部与半导体本体的侧部之间的界面变化的第二半导体材料的浓度

公开(公告)号：US20070210301A1

公开(公告)日：2007-09-13

申请号：US11371544

申请日：2006-03-09

Applicant: Jin-Ping Han

Inventor： Jin-Ping Han

IPC: H01L29/06 ,  H01L31/117

CPC classification number: H01L29/7834 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.

Abstract translation: 公开了半导体器件及其制造方法。 优选实施例包括包括工件的半导体器件，所述工件包括第一区域和靠近第一区域的第二区域。 第一材料设置在第一区域中，并且第二材料的至少一个区域设置在第一区域内的第一材料内，第二材料包括与第一材料不同的材料。 第二材料的至少一个区域增加第一区域的第一应力。

公开(公告)号：US09142547B2

公开(公告)日：2015-09-22

申请号：US13077554

申请日：2011-03-31

Applicant: Knut Stahrenberg ,  Jin-Ping Han

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/8238

CPC classification number: H01L27/0629 ,  H01L21/823814 ,  H01L28/20

Abstract: A semiconductor device includes a semiconductor body of a first semiconductive material. A transistor is disposed in the semiconductor body. The transistor includes source and drain regions of a second semiconductive material embedded in the semiconductor body. A resistor overlies a top surface of the semiconductor body and is laterally spaced from the transistor. The resistor is formed from the second semiconductive material.

Abstract translation: 半导体器件包括第一半导体材料的半导体本体。 晶体管设置在半导体本体中。 晶体管包括嵌入半导体本体中的第二半导体材料的源区和漏区。 电阻器覆盖半导体主体的顶表面并与晶体管横向间隔开。 电阻器由第二半导体材料形成。

公开(公告)号：US08198194B2

公开(公告)日：2012-06-12

申请号：US12729486

申请日：2010-03-23

Applicant: Jong Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

Inventor： Jong Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

IPC: H01L21/311

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

Abstract: Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.

Abstract translation: 形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。 这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。 然后在栅电极上图案化掩模层。 选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。 然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。 在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。 然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

公开(公告)号：US07892939B2

公开(公告)日：2011-02-22

申请号：US12043384

申请日：2008-03-06

Applicant: Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

Inventor： Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

IPC: H01L21/76 ,  H01L21/311

CPC classification number: H01L21/76262 ,  H01L21/76278

Abstract: The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.

Abstract translation: 公开了STI模型中的有源面积损耗的防止，这导致根据工艺流程制造的器件中的器件性能提高。 多个不同实施例中通常共享的方法将当前常规STI结构转换为绝缘体用锥形图案化的工艺流程。 在锥形沟槽中的绝缘体的表面下方形成偏析层。 然后用半导体材料填充锥形沟槽，半导体材料被进一步处理以产生多个有源器件。 因此，有源器件是在图案化电介质中产生的，而不是在有源器件的半导体衬底中产生的STI。

公开(公告)号：US20100308418A1

公开(公告)日：2010-12-09

申请号：US12481373

申请日：2009-06-09

Applicant: Knut Stahrenberg ,  Roland Hampp ,  Jin-Ping Han ,  Klaus von Arnim

Inventor： Knut Stahrenberg ,  Roland Hampp ,  Jin-Ping Han ,  Klaus von Arnim

IPC: H01L27/088 ,  H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a gate dielectric and a cap layer disposed over the gate dielectric. The first transistor includes a gate including a metal layer disposed over the cap layer and a semiconductive material disposed over the metal layer. The semiconductor device includes a second transistor in a second region of the workpiece, which includes the gate dielectric and the cap layer disposed over the gate dielectric. The second transistor includes a gate that includes the metal layer disposed over the cap layer and the semiconductive material disposed over the metal layer. A thickness of the metal layer, a thickness of the semiconductive material, an implantation region of a channel region, or a doped region of the gate dielectric of the first transistor achieves a predetermined threshold voltage for the first transistor.

Abstract translation: 公开了半导体器件及其制造方法。 在一个实施例中，半导体器件包括具有栅极电介质的第一晶体管和设置在栅极电介质上的覆盖层。 第一晶体管包括包括设置在盖层上的金属层的栅极和设置在金属层上的半导体材料。 半导体器件包括在工件的第二区域中的第二晶体管，其包括设置在栅极电介质上的栅极电介质和盖层。 第二晶体管包括栅极，其包括设置在覆盖层上的金属层和设置在金属层上的半导体材料。 第一晶体管的金属层的厚度，半导体材料的厚度，沟道区的注入区域或栅极电介质的掺杂区域实现了第一晶体管的预定阈值电压。

公开(公告)号：US20100289088A1

公开(公告)日：2010-11-18

申请号：US12465908

申请日：2009-05-14

Applicant: Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Jin-Ping Han ,  Yong Meng Lee

Inventor： Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Jin-Ping Han ,  Yong Meng Lee

IPC: H01L27/088 ,  H01L21/8236

CPC classification number: H01L21/823807

Abstract: An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.

Abstract translation: 可以在为p型场效应晶体管保留的第一区域中形成外延半导体层。 形成离子注入掩模层并图案化以在第一区域中提供开口，同时阻挡至少为n型场效应晶体管保留的第二区域。 将氟注入到开口中以在第一区域中形成外延氟掺杂半导体层和下面的掺氟半导体层。 在第一和第二区域中形成包括高k栅极电介质层和调整氧化物层的复合栅极堆叠。 P型和n型场效应晶体管（FET）分别形成在第一和第二区域中。 外延氟掺杂半导体层和下面的掺氟半导体层通过直接在上面的调整氧化物部分来补偿p-FET中阈值电压的降低。