公开(公告)号：US08872270B2

公开(公告)日：2014-10-28

申请号：US13686212

申请日：2012-11-27

Applicant: Kilho Lee ,  Ki Joon Kim ,  Se-Woong Park

Inventor： Kilho Lee ,  Ki Joon Kim ,  Se-Woong Park

IPC: H01L21/70 ,  H01L29/82 ,  H01L27/108

CPC classification number: H01L43/12 ,  H01L27/10888 ,  H01L27/222 ,  H01L27/228 ,  H01L29/82

Abstract: Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.

Abstract translation: 存储器件及其制造方法包括：包括单元区域和外围电路区域的衬底，在单元区域上的数据存储，在数据存储器上并耦合到数据存储器的第一位线，耦合到外围电路区域上的外围晶体管的第一触点 以及在第一触点上并耦合到第一触点的第二位线。 第二位线可以各自具有低于数据存储器的最低表面的最下表面。

公开(公告)号：US20140117560A1

公开(公告)日：2014-05-01

申请号：US14053932

申请日：2013-10-15

Applicant: Kil-Ho Lee ,  Se-Woong Park ,  Ki-Joon Kim

Inventor： Kil-Ho Lee ,  Se-Woong Park ,  Ki-Joon Kim

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/7681 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in the layer, and a mask layer is formed in the first trench. The mask layer has a first thickness from a bottom surface of the first trench to the top of the mask layer. The mask layer is patterned to form a mask that at least partially exposes a sidewall of the first trench. A portion of the mask adjacent to the exposed sidewall of the first trench has a second thickness smaller than the first thickness. The layer is etched to form a second trench using the mask as an etching mask. The second trench is in fluid communication with the first trench. A conductive pattern is formed in the first trench and the second trench.

Abstract translation: 公开了一种半导体器件和形成半导体器件的方法。 在该方法中，在衬底上形成诸如绝缘中间层的层。 在该层中形成第一沟槽，并且在第一沟槽中形成掩模层。 掩模层具有从第一沟槽的底表面到掩模层的顶部的第一厚度。 图案化掩模层以形成至少部分地暴露第一沟槽的侧壁的掩模。 与第一沟槽的暴露的侧壁相邻的掩模的一部分具有小于第一厚度的第二厚度。 使用掩模作为蚀刻掩模蚀刻该层以形成第二沟槽。 第二沟槽与第一沟槽流体连通。 在第一沟槽和第二沟槽中形成导电图案。

公开(公告)号：US20130221417A1

公开(公告)日：2013-08-29

申请号：US13686212

申请日：2012-11-27

Applicant: Kilho LEE ,  Ki Joon KIM ,  Se-Woong PARK

Inventor： Kilho LEE ,  Ki Joon KIM ,  Se-Woong PARK

IPC: H01L29/82

CPC classification number: H01L43/12 ,  H01L27/10888 ,  H01L27/222 ,  H01L27/228 ,  H01L29/82

Abstract: Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.

公开(公告)号：US08117740B2

公开(公告)日：2012-02-21

申请号：US11996413

申请日：2006-07-24

Applicant: Ki-Joon Kim ,  Yong-Hwi Jo ,  Sung-Young Oh ,  Jun-Tae Hwang

Inventor： Ki-Joon Kim ,  Yong-Hwi Jo ,  Sung-Young Oh ,  Jun-Tae Hwang

IPC: G01R3/00 ,  B23P19/00

CPC classification number: G01R3/00 ,  G01R1/07342 ,  Y10T29/49133 ,  Y10T29/49137 ,  Y10T29/49147 ,  Y10T29/49222 ,  Y10T29/53004 ,  Y10T29/53039 ,  Y10T29/53061 ,  Y10T29/53174 ,  Y10T29/53191 ,  Y10T29/53265

Abstract: In a method of manufacturing a probe card, a plurality of probe modules, including a sacrificial substrate and probes on the sacrificial substrate, is prepared. The probe modules are mutually aligned to form a probe module assembly having the aligned probe modules and a desired size. The probe module assembly is then attached to a probe substrate. Thus, the probe card having a large size may be manufactured.

Abstract translation: 在制造探针卡的方法中，准备了包括牺牲衬底和牺牲衬底上的探针的多个探针模块。 探针模块相互对准以形成具有对准的探针模块和所需尺寸的探针模块组件。 然后将探针模块组件附接到探针衬底。 因此，可以制造具有大尺寸的探针卡。

公开(公告)号：US08116125B2

公开(公告)日：2012-02-14

申请号：US12081451

申请日：2008-04-16

Applicant: Cheol-kyu Kim ,  Yoon-ho Khang ,  Ki-joon Kim

Inventor： Cheol-kyu Kim ,  Yoon-ho Khang ,  Ki-joon Kim

IPC: G11C7/00 ,  G11C7/12 ,  G11C11/00 ,  G11C7/22 ,  G11C11/21

CPC classification number: G11C11/5678 ,  G11C13/0004

Abstract: A method of operating a phase-change memory device, including a phase-change layer and a unit applying a voltage to the phase-change layer, which includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.

Abstract translation: 一种操作相变存储器件的方法，包括相变层和向相变层施加电压的单元，其包括向相变层施加复位电压，其中复位电压至少包括 连续施加的两个脉冲电压。

公开(公告)号：US07678587B2

公开(公告)日：2010-03-16

申请号：US11990275

申请日：2006-08-02

Applicant: Ki-Joon Kim ,  Yong-Hwi Jo

Inventor： Ki-Joon Kim ,  Yong-Hwi Jo

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R1/06727 ,  G01R3/00 ,  Y10T29/49004

Abstract: Disclosed is a cantilever-type probe and methods of fabricating the same. The probe is comprised of a cantilever being longer lengthwise relative to the directions of width and height, and a tip extending from the bottom of the cantilever and formed at an end of the cantilever. A section of the tip parallel to the bottom of the cantilever is rectangular, having four sides slant to the lengthwise direction of the cantilever.

Abstract translation: 公开了一种悬臂式探针及其制造方法。 探头由相对于宽度和高度方向的纵向长度的悬臂组成，以及从悬臂的底部延伸并形成在悬臂的端部处的尖端。 平行于悬臂底部的尖端的一部分是矩形的，具有沿着悬臂的长度方向倾斜的四个边。

公开(公告)号：US20090303226A1

公开(公告)日：2009-12-10

申请号：US12541236

申请日：2009-08-14

Applicant: KI-JOON KIM

Inventor： KI-JOON KIM

IPC: G06F3/038

CPC classification number: G09G3/3688 ,  G09G2310/0291 ,  G09G2310/08

Abstract: There is provided a source driver capable of controlling the timing of source line driving signals in a liquid crystal display device. The source driver includes a plurality of output circuits, each output circuit including an output buffer and a switch. The output buffer amplifies an analog image signal, and the switch outputs the amplified analog image signal as a source line driving signal in response to a control signal. The source driver further comprises a control circuit for generating the control signal, the control circuit comprising: a delay circuit delaying a switch signal and generating a delayed switch signal; and a multiplexer selecting one of the switch signal and the delayed switch signal in response to a selection signal and outputting the selected signal as the control signal.

Abstract translation: 提供了能够控制液晶显示装置中的源极线驱动信号的定时的源极驱动器。 源极驱动器包括多个输出电路，每个输出电路包括输出缓冲器和开关。 输出缓冲器放大模拟图像信号，并且开关响应于控制信号而输出放大的模拟图像信号作为源极线驱动信号。 源极驱动器还包括用于产生控制信号的控制电路，所述控制电路包括：延迟电路，延迟开关信号并产生延迟的开关信号; 以及多路复用器，响应于选择信号选择开关信号和延迟开关信号之一，并输出所选择的信号作为控制信号。

公开(公告)号：US07573058B2

公开(公告)日：2009-08-11

申请号：US11509001

申请日：2006-08-24

Applicant: Jin-seo Noh ,  Ki-joon Kim ,  Yoon-ho Khang

Inventor： Jin-seo Noh ,  Ki-joon Kim ,  Yoon-ho Khang

IPC: H01L29/02

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625

Abstract: A phase change memory device includes a switch and a storage node connected to the switch. The storage node includes a first electrode, a phase change layer and a second electrode. The phase change layer is formed of an InSbTe compound doped with Ge. In a method of operating a phase change memory including a switch and a storage node, the switch is maintained in an on state, and a first current is applied to the storage node.

Abstract translation: 相变存储器件包括开关和连接到开关的存储节点。 存储节点包括第一电极，相变层和第二电极。 相变层由掺杂有Ge的InSbTe化合物形成。 在操作包括开关和存储节点的相变存储器的方法中，将开关保持在接通状态，并且将第一电流施加到存储节点。

公开(公告)号：US20090141546A1

公开(公告)日：2009-06-04

申请号：US12081451

申请日：2008-04-16

Applicant: Cheol-kyu Kim ,  Yoon-ho Khang ,  Ki-joon Kim

Inventor： Cheol-kyu Kim ,  Yoon-ho Khang ,  Ki-joon Kim

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C13/0004

Abstract: A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.

Abstract translation: 提供一种操作包括相变层和向相变层施加电压的单元的相变存储器件的方法。 该方法包括将复位电压施加到相变层，其中复位电压包括连续施加的至少两个脉冲电压。

公开(公告)号：US20070200108A1

公开(公告)日：2007-08-30

申请号：US11654004

申请日：2007-01-17

Applicant: Jin-Seo Noh ,  Ki-Joon Kim

Inventor： Jin-Seo Noh ,  Ki-Joon Kim

IPC: H01L47/00

CPC classification number: H01L45/12 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16

Abstract: A storage node, a phase change random access memory having an improved structure to improve adhesion of a phase change material layer and methods of fabricating the same are provided. The storage node may include a bottom electrode, a top electrode, a phase change material layer inserted between the bottom electrode and the top electrode, and an adhesion interfacial layer inserted between the bottom electrode and the phase change material layer. The phase change random access memory may include a switching device and the storage node connected to the switching device.

Abstract translation: 提供存储节点，具有改进的结构以改善相变材料层的粘附性的相变随机存取存储器及其制造方法。 存储节点可以包括底部电极，顶部电极，插入在底部电极和顶部电极之间的相变材料层，以及插入在底部电极和相变材料层之间的粘合界面层。 相变随机存取存储器可以包括交换设备和连接到交换设备的存储节点。