公开(公告)号：US07553763B2

公开(公告)日：2009-06-30

申请号：US11463012

申请日：2006-08-08

Applicant: Tsai-Fu Hsiao ,  Chin-Cheng Chien ,  Kuo-Tai Huang

Inventor： Tsai-Fu Hsiao ,  Chin-Cheng Chien ,  Kuo-Tai Huang

IPC: H01L21/20

CPC classification number: H01L21/28518 ,  H01L21/26506 ,  H01L21/28052 ,  H01L29/665 ,  H01L29/6656

Abstract: A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process to form an amorphized layer in the predetermined salicide region of the silicon substrate near, forming a metal layer on the surface of the amorphized layer, and reacting the metal layer with the amorphized layer to form a silicide layer on the surface of the silicon substrate.

Abstract translation: 自对准硅化物工艺包括提供包括至少预定的自对准硅化物区域的硅衬底，进行聚簇离子注入工艺以在硅衬底的预定自对准硅化物区域中形成非晶化层，在非晶化层的表面上形成金属层 并使金属层与非晶化层反应，以在硅衬底的表面上形成硅化物层。

公开(公告)号：US20070102774A1

公开(公告)日：2007-05-10

申请号：US11164025

申请日：2005-11-08

Applicant: Yun-Ren Wang ,  Ying-Wei Yen ,  Shu-Yen Chan ,  Kuo-Tai Huang

Inventor： Yun-Ren Wang ,  Ying-Wei Yen ,  Shu-Yen Chan ,  Kuo-Tai Huang

IPC: H01L29/78 ,  H01L21/4763

CPC classification number: H01L21/28202 ,  H01L21/28088 ,  H01L21/76822 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases and then decreases toward the substrate with the maximum concentration of nitrogen in the sacrificial oxide layer. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.

Abstract translation: 提供一种制造栅极结构的方法。 首先，在基板上形成牺牲氧化物层。 进行氮化处理工艺以重新分配牺牲层和衬底中的氮原子，并产生浓度分布，使得氮的浓度逐渐增加，然后在牺牲氧化物层中具有氮的最大浓度朝向衬底减小。 接下来，除去牺牲氧化物层。 进行再氧化处理以在衬底的表面上产生界面层。 在基板上依次形成高K（介电常数）栅介质层，阻挡层和金属层。 限定金属层，势垒层，高K栅极介电层和界面层以形成层叠栅极结构。

公开(公告)号：US06555485B1

公开(公告)日：2003-04-29

申请号：US10055891

申请日：2002-01-28

Applicant: Chuan-Hsi Liu ,  Hsiu-Shan Lin ,  Yu-Yin Lin ,  Tung-Ming Pan ,  Kuo-Tai Huang

Inventor： Chuan-Hsi Liu ,  Hsiu-Shan Lin ,  Yu-Yin Lin ,  Tung-Ming Pan ,  Kuo-Tai Huang

IPC: H01L2131

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/51 ,  H01L29/518

Abstract: This invention relates to a method for forming a gate dielectric layer, and, more particularly, to a method for treating a base oxide layer by using a remote plasma nitridation procedure and a thermal annealing treatment in turn to form the gate dielectric layer. The first step of the present invention is to form a base oxide layer on a substrate of a wafer. The base oxide layer can be formed using any kind of method. Then nitrogen ions are introduced into the base oxide layer using the remote plasma nitridation procedure to form a remote plasma nitrided oxide layer. Finally, the wafer is placed in a reaction chamber which comprises oxygen (O2) or nitric monoxide (NO) to treat the remote plasma nitrided oxide layer using the thermal annealing procedure and the gate dielectric layer of the present invention is formed.

Abstract translation: 本发明涉及一种用于形成栅极电介质层的方法，更具体地，涉及一种通过使用远程等离子体氮化处理和热退火处理依次形成栅极介电层来处理基底氧化物层的方法。 本发明的第一步是在晶片的基片上形成基底氧化物层。 基底氧化物层可以使用任何种类的方法形成。 然后使用远程等离子体氮化方法将氮离子引入基底氧化物层中以形成远程等离子体氮化氧化物层。 最后，将晶片放置在包含氧（O 2）或一氧化氮（NO）的反应室中，以使用热退火程序处理远程等离子体氮化氧化物层，并形成本发明的栅介质层。

公开(公告)号：US06368923B1

公开(公告)日：2002-04-09

申请号：US09561577

申请日：2000-04-28

Applicant: Kuo-Tai Huang

Inventor： Kuo-Tai Huang

IPC: H01L218234

CPC classification number: H01L21/823462 ,  H01L21/82345

Abstract: A method of fabricating a dual metal gate. A cell region and a peripheral region are formed on a substrate, and a first dummy gate electrode and a second dummy gate electrode are formed on the substrate, respectively, in the cell region and in the peripheral region. A patterned first dielectric layer is formed above the substrate, and the layer exposes the surfaces of the first dummy gate electrode and the second dummy gate electrode. The first dummy gate electrode and the second dummy gate electrode are then removed to expose the substrate, and an oxide layer is formed on the exposed substrate in the peripheral region. A remote plasma nitridation step is performed to nitridate the surface of the exposed substrate in the cell region and to nitridate the oxide layer into a material layer in the peripheral region. A second dielectric layer and a conducting layer are formed sequentially above the substrate. The conducting layer fills up the trenches that are formed by removing the first dummy gate electrode and the second dummy gate electrode. A part of the second dielectric layer and a part of the conducting layer are removed until the surface of the first dielectric layer is exposed, and a dual metal gate is completed thereon.

Abstract translation: 一种制造双金属栅极的方法。 在基板上形成单元区域和周边区域，并且在单元区域和周边区域中分别在基板上形成第一伪栅极电极和第二伪栅极电极。 在衬底上形成图案化的第一电介质层，并且该层露出第一虚拟栅极电极和第二虚拟栅电极的表面。 然后去除第一伪栅极电极和第二虚拟栅极电极以露出衬底，并且在外围区域中的暴露的衬底上形成氧化物层。 进行远程等离子体氮化步骤以使细胞区域中暴露的基底的表面氮化，并将氧化物层氮化为外围区域中的材料层。 在衬底上顺序地形成第二电介质层和导电层。 导电层填充通过去除第一伪栅极电极和第二虚拟栅极电极而形成的沟槽。 去除第二电介质层的一部分和导电层的一部分直到第一介电层的表面露出，并且在其上完成双金属栅极。

公开(公告)号：US6037206A

公开(公告)日：2000-03-14

申请号：US080116

申请日：1998-05-15

Applicant: Kuo-Tai Huang ,  Hsi-Ta Chuang ,  Tri-Rung Yew

Inventor： Kuo-Tai Huang ,  Hsi-Ta Chuang ,  Tri-Rung Yew

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method for fabricating a capacitor of a DRAM includes a lower conductive layer of the capacitor is formed over a substrate and is electrically coupled to an interchangeable source/drain region through a contact window penetrating an insulating layer. Then performing etching process on the lower conductive layer so as to form a fence-like plate with a higher height than a thickness of the lower conductive layer and adhere to the lower conductive layer. Next a media conductive layer is formed over the lower conductive layer and the fence-like plate. Then the technology of etching back is utilized to round the sharp area on the tip of the fence-like plate. The lower conductive layer and the media conductive layer are electrically coupled together as a lower electrode. Then, a dielectric thin film is formed over the media conductive layer and an upper electrode is formed over the dielectric thin film. Therefore, a MIM capacitor according to the preferred embodiment of the invention is formed.

Abstract translation: 一种用于制造DRAM电容器的方法包括：电容器的下导电层形成在衬底上，并通过穿透绝缘层的接触窗电耦合到可互换的源/漏区。 然后对下导电层进行蚀刻处理，以形成具有比下导电层的厚度高的高度的栅栏状的板，并粘附到下导电层。 接下来，在下导电层和栅栏状板上形成介质导电层。 然后，利用蚀刻技术来围绕栅栏状板的尖端上的尖锐区域。 下导电层和介质导电层作为下电极电耦合在一起。 然后，在介质导电层上形成电介质薄膜，在电介质薄膜上方形成上电极。 因此，形成根据本发明的优选实施例的MIM电容器。

公开(公告)号：US08536660B2

公开(公告)日：2013-09-17

申请号：US12047113

申请日：2008-03-12

Applicant: Peng-Fu Hsu ,  Yong-Tian Hou ,  Ssu-Yi Li ,  Kuo-Tai Huang ,  Mong Song Liang

Inventor： Peng-Fu Hsu ,  Yong-Tian Hou ,  Ssu-Yi Li ,  Kuo-Tai Huang ,  Mong Song Liang

IPC: H01L21/02

CPC classification number: H01L21/823857 ,  H01L21/823842 ,  H01L27/092

Abstract: A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer.

Abstract translation: 半导体结构包括包括第一栅极的第一MOS器件和包括第二栅极的第二MOS器件。 第一栅极包括在半导体衬底上的第一高k电介质; 第一高k电介质上的第二高k电介质; 在所述第二高k电介质上的第一金属层，其中所述第一金属层支配所述第一MOS器件的功函数; 以及在所述第一金属层上的第二金属层。 第二栅极包括半导体衬底上的第三高k电介质，其中第一和第三高k电介质由相同的材料形成，并具有基本上相同的厚度; 在所述第三高k电介质上的第三金属层，其中所述第三金属层和所述第二金属层由相同的材料形成，并且具有基本相同的厚度; 以及在第三金属层上的第四金属层。

公开(公告)号：US08524588B2

公开(公告)日：2013-09-03

申请号：US12492889

申请日：2009-06-26

Applicant: Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Donald Y. Chao ,  Yi-Shien Mor ,  Kuo-Tai Huang

Inventor： Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Donald Y. Chao ,  Yi-Shien Mor ,  Kuo-Tai Huang

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在半导体衬底上形成栅极电介质，在栅极电介质上或之下形成覆盖层，在覆盖层上形成金属层，金属层具有第一功函数，处理金属层的一部分，使得 所述金属层的所述部分的功函数从所述第一功函数变化为第二功函数，并且从具有所述第一功函数的所述金属层的未处理部分形成第一金属栅极，并且从所述处理的所述第二金属栅极形成第二金属栅极 具有第二功函数的金属层的部分。

公开(公告)号：US08193586B2

公开(公告)日：2012-06-05

申请号：US12389535

申请日：2009-02-20

Applicant: Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang ,  Chien-Liang Chen

Inventor： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang ,  Chien-Liang Chen

IPC: H01L21/02 ,  H01L21/8238

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract translation: 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US20120086085A1

公开(公告)日：2012-04-12

申请号：US13329877

申请日：2011-12-19

Applicant: Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

Inventor： Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L29/49 ,  H01L29/51

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，在第一区域的高k电介质层上形成覆盖层，形成第一金属层 在第一区域中的覆盖层和第二区域中的高k电介质之上，然后在第一区域中形成第一栅极堆叠，在第二区域中形成第二栅极叠层，保护第一栅极叠层中的第一金属层，同时 对所述第二栅极堆叠中的所述第一金属层进行处理工艺，以及在所述第一栅极堆叠中的所述第一金属层上方以及所述第二栅极堆叠中经处理的第一金属层之上形成第二金属层。

公开(公告)号：US07829949B2

公开(公告)日：2010-11-09

申请号：US12589421

申请日：2009-10-23

Applicant: Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

Inventor： Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

IPC: H01L27/092

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric.