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    Shallow trench isolation fill by liquid phase deposition of SiO2
    41.
    发明授权
    Shallow trench isolation fill by liquid phase deposition of SiO2 有权
    浅沟槽隔离填充SiO 2的液相沉积

    公开(公告)号：US07525156B2

    公开(公告)日：2009-04-28

    申请号：US11760477

    申请日：2007-06-08

    申请人： Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

    发明人： Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

    IPC分类号： H01L23/58

    CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/84

    摘要： To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

    摘要翻译： 为了隔离形成在绝缘体上硅（SOI）衬底上的两个有源区，浅沟槽隔离区填充有液相沉积二氧化硅（LPD-SiO 2），同时避免用氧化物覆盖有源区。 通过以这种方式选择性地沉积氧化物，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。 另外，LPD-SiO2不包括CVD二氧化硅的生长接缝。 因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空腔和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过其它氧化物区域的蚀刻速率。

    Horizontal memory gain cells
    45.
    发明授权
    Horizontal memory gain cells 失效
    水平记忆增益细胞

    公开(公告)号：US07109546B2

    公开(公告)日：2006-09-19

    申请号：US10879815

    申请日：2004-06-29

    申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

    发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

    IPC分类号： H01L31/119

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  G11C2213/17 ,  H01L27/108 ,  H01L27/10861 ,  H01L27/10873 ,  Y10S977/742

    摘要： A gain cell for a memory circuit, a memory circuit formed from multiple gain cells, and methods of fabricating such gain cells and memory circuits. The memory gain cell includes a storage capacitor, a write device electrically coupled with the storage capacitor for charging and discharging the storage capacitor to define a stored electrical charge, and a read device. The read device includes one or more semiconducting carbon nanotubes each electrically coupled between a source and drain. A portion of each semiconducting carbon nanotube is gated by the read gate and the storage capacitor to thereby regulate a current flowing through each semiconducting carbon nanotube from the source to the drain. The current is proportional to the electrical charge stored by the storage capacitor. In certain embodiments, the memory gain cell may include multiple storage capacitors.

    摘要翻译： 用于存储器电路的增益单元，由多个增益单元形成的存储器电路，以及制造这种增益单元和存储器电路的方法。 存储增益单元包括存储电容器，与存储电容器电耦合以对存储电容器进行充电和放电以定义存储的电荷的写入装置和读取装置。 读取装置包括一个或多个半导体碳纳米管，每个碳纳米管电耦合在源极和漏极之间。 每个半导体碳纳米管的一部分由读取栅极和存储电容器选通，从而调节从源极到漏极流过每个半导体碳纳米管的电流。 电流与存储电容器存储的电荷成比例。 在某些实施例中，存储增益单元可以包括多个存储电容器。

    Method of forming FinFET gates without long etches
    47.
    发明授权
    Method of forming FinFET gates without long etches 有权
    在没有长时间刻蚀的情况下形成FinFET栅极的方法

    公开(公告)号：US06989308B2

    公开(公告)日：2006-01-24

    申请号：US10798907

    申请日：2004-03-11

    申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Hofak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

    发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Hofak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831

    摘要： A method for forming a gate for a FinFET uses a series of selectively deposited sidewalls along with other sacrificial layers to create a cavity in which a gate can be accurately and reliably formed. This technique avoids long directional etching steps to form critical dimensions of the gate that have contributed to the difficulty of forming FinFETs using conventional techniques. In particular, a sacrificial seed layer, from which sidewalls can be accurately grown, is first deposited over a silicon fin. Once the sacrificial seed layer is etched away, the sidewalls can be surrounded by another disposable layer. Etching away the sidewalls will result in cavities being formed that straddle the fin, and gate conductor material can then be deposited within these cavities. Thus, the height and thickness of the resulting FinFET gate can be accurately controlled by avoiding a long direction etch down the entire height of the fin.

    摘要翻译： 用于形成用于FinFET的栅极的方法使用一系列选择性沉积的侧壁与其它牺牲层一起形成可以准确可靠地形成栅极的空腔。 该技术避免了长时间的定向蚀刻步骤，以形成使用常规技术有助于形成FinFET的困难的栅极的临界尺寸。 特别地，首先在硅片上沉积可以精确地生长侧壁的牺牲种子层。 一旦牺牲种子层被蚀刻掉，侧壁可以被另一个一次性层包围。 蚀刻侧壁将导致跨过翅片形成的空腔，然后栅极导体材料可以沉积在这些空腔内。 因此，通过避免沿翅片的整个高度的长方向蚀刻，可以精确地控制所得FinFET栅极的高度和厚度。

    Dual gated finfet gain cell
    48.
    发明授权
    Dual gated finfet gain cell 有权
    双门控finfet增益单元

    公开(公告)号：US06970372B1

    公开(公告)日：2005-11-29

    申请号：US10879833

    申请日：2004-06-29

    申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

    发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

    IPC分类号： G11C7/00 ,  H01L27/108

    CPC分类号： H01L27/108 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

    摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.

    摘要翻译： 用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。 存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。 读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。 第一栅电极与存储装置电耦合。 第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。 当门控时，电流的大小取决于存储设备存储的电量。