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公开(公告)号：US08125049B2
公开(公告)日：2012-02-28
申请号：US12618830
申请日：2009-11-16
CPC分类号： H01L27/0629 , H01L28/60
摘要： A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.
摘要翻译： 电容器结构包括半导体衬底; 位于所述半导体衬底上的第一电容器板，所述第一电容器板包括具有周围间隔物的多晶硅结构; 硅化物层，形成在所述第一电容器板的上表面的第一部分中; 电容器电介质层，形成在第一电容器板的上表面的第二部分上并且横向延伸超过间隔物以接触半导体衬底; 在层间电介质（ILD）中的接触，接触硅化物层的接触和ILD上的第一金属层; 以及在所述电容器电介质层上的第二电容器板，其中由所述第一电容器板，所述电容器介电层和所述第二电容器板以及金属 - 绝缘体 - 半导体（MIS）电容器形成金属 - 绝缘体 - 金属（MIM）电容器 由第二电容器板，电容器电介质层和半导体衬底形成。
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42.发明申请ASYMMETRIC SILICON-ON-INSULATOR (SOI) JUNCTION FIELD EFFECT TRANSISTOR (JFET), A METHOD OF FORMING THE ASYMMETRICAL SOI JFET, AND A DESIGN STRUCTURE FOR THE ASYMMETRICAL SOI JFET 有权不对称硅绝缘体（SOI）结场效应晶体管（JFET），形成非对称SOI JFET的方法和非对称SOI JFET的设计结构公开(公告)号：US20110284930A1
公开(公告)日：2011-11-24
申请号：US12784583
申请日：2010-05-21
申请人： Douglas B. Hershberger , Richard A. Phelps , Robert M. Rassel , Stephen A. St. Onge , Michael J. Zierak
发明人： Douglas B. Hershberger , Richard A. Phelps , Robert M. Rassel , Stephen A. St. Onge , Michael J. Zierak
IPC分类号： H01L29/812 , H01L21/782 , G06F17/50 , H01L27/12
CPC分类号： G06F17/5068 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0843 , H01L29/66901 , H01L29/8086
摘要： An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).
摘要翻译： 不对称绝缘体上硅（SOI）结场效应晶体管（JFET）及其方法。 JFET包括在绝缘体层上的底栅极，底栅上的沟道区，以及沟道区上的源/漏区和源/漏区之间的顶栅。 STI将源极/漏极区域与顶部栅极隔离，并且DTI横向围绕JFET以将其与其它器件隔离。 非环形阱位于与沟道区域和底部栅极相邻的位置（例如，具有与顶部和底部栅极相同的导电类型的阱可以连接到顶部栅极并且可以向下延伸到绝缘体层，形成 在沟道区域的仅一部分上的栅极接触和/或具有与沟道和源极/漏极区相同的导电类型的另一个阱可以从源极区域延伸到绝缘体层，形成源极至沟道的带） 。
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公开(公告)号：US07994895B2
公开(公告)日：2011-08-09
申请号：US11777389
申请日：2007-07-13
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
IPC分类号： H01C1/08
CPC分类号： H01C7/1013 , H01C1/084 , H01L2924/0002 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49144 , Y10T29/49147 , H01L2924/00
摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
摘要翻译： 提供带散热片的电阻。 散热器包括具有导热性高的金属或其它热导体的导电路径。 为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。 因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。 除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。
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44.发明授权Methods of forming a hyper-abrupt P-N junction and design structures for an integrated circuit 有权形成超突变P-N结的方法和集成电路的设计结构公开(公告)号：US07989302B2
公开(公告)日：2011-08-02
申请号：US12795108
申请日：2010-06-07
申请人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
IPC分类号： H01L21/20
CPC分类号： H01L29/93
摘要： Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt p-n junction.
摘要翻译： 形成超突变p-n结的方法和包含具有超突变p-n结的器件结构的集成电路的设计结构。 通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。 反渗透定义了超突变p-n结。 在离子注入期间，在器件层的顶表面上承载的栅结构作为硬掩模进行操作，以有助于限定超突变p-n结的横向边界。
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公开(公告)号：US20110156223A1
公开(公告)日：2011-06-30
申请号：US12647796
申请日：2009-12-28
申请人： Renata A. Camillo-Castillo , Robert J. Gauthier, JR. , Richard A. Phelps , Robert M. Rassel , Andreas D. Stricker
发明人： Renata A. Camillo-Castillo , Robert J. Gauthier, JR. , Richard A. Phelps , Robert M. Rassel , Andreas D. Stricker
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/8086 , H01L21/76283 , H01L29/66901 , H01L29/7846
摘要： An integrated circuit (IC) chip is provided comprising at least one trench including a stress-inducing material which imparts a stress on a channel region of a device, such as a junction gate field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). A related method is also disclosed.
摘要翻译： 提供了一种集成电路（IC）芯片，其包括至少一个沟槽，该至少一个沟槽包括在器件的沟道区域上施加应力的应力诱导材料，诸如结栅场效应晶体管（JFET）或金属氧化物 - 半导体场效应晶体管（MOSFET）。 还公开了相关方法。
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公开(公告)号：US20110115005A1
公开(公告)日：2011-05-19
申请号：US12618830
申请日：2009-11-16
CPC分类号： H01L27/0629 , H01L28/60
摘要： A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.
摘要翻译： 电容器结构包括半导体衬底; 位于所述半导体衬底上的第一电容器板，所述第一电容器板包括具有周围间隔物的多晶硅结构; 硅化物层，形成在所述第一电容器板的上表面的第一部分中; 电容器电介质层，形成在第一电容器板的上表面的第二部分上并且横向延伸超过间隔物以接触半导体衬底; 在层间电介质（ILD）中的接触，接触硅化物层的接触和ILD上的第一金属层; 以及在所述电容器电介质层上的第二电容器板，其中由所述第一电容器板，所述电容器介电层和所述第二电容器板以及金属 - 绝缘体 - 半导体（MIS）电容器形成金属 - 绝缘体 - 金属（MIM）电容器 由第二电容器板，电容器电介质层和半导体衬底形成。
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47.发明授权公开(公告)号：US07936041B2
公开(公告)日：2011-05-03
申请号：US11853973
申请日：2007-09-12
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L21/8249 , H01L27/0635 , H01L27/0814 , H01L29/161 , H01L29/47 , H01L29/66143
摘要： The structure for millimeter-wave frequency applications, includes a Schottky barrier diode (SBD) with a cutoff frequency (FC) above 1.0 THz formed on a SiGe BiCMOS wafer. A method is also contemplated for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.
摘要翻译： 毫米波频率应用的结构包括在SiGe BiCMOS晶片上形成的截止频率（FC）大于1.0THz的肖特基势垒二极管（SBD）。 还考虑了在SiGe BiCMOS晶片上形成肖特基势垒二极管的方法，包括形成提供高于约1.0THz的截止频率（Fc）的结构。 在实施例中，提供高于约1.0THz的截止频率（Fc）的结构可以包括具有提供高于约1.0THz的截止频率（FC）的阳极区域的阳极，具有提供截止频率 频率（FC）高于约1.0THz，在提供高于约1.0THz的截止频率（FC）的能量和剂量下的p型防护，所述p型护罩具有提供高于约截止频率（FC）的尺寸 1.0 THz，以及具有n型掺杂剂的良好裁缝，其提供高于约1.0THz的截止频率（FC）。
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公开(公告)号：US07910450B2
公开(公告)日：2011-03-22
申请号：US11276282
申请日：2006-02-22
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , John E. Florkey , Heidi L. Greer , Robert M. Rassel , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , John E. Florkey , Heidi L. Greer , Robert M. Rassel , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L21/20
CPC分类号： H01L29/8605 , H01L27/0802 , H01L28/20
摘要： The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.
摘要翻译： 本发明提供一种包括具有改进控制的掩埋电阻器的半导体结构，其中电阻器制造在半导体衬底的也存在于衬底中的阱区域下方的区域中。 根据本发明，本发明的结构包括至少含有一个阱区的半导体衬底; 以及位于半导体衬底的位于所述阱区之下的区域中的掩埋电阻器。 本发明还提供一种制造这样的结构的方法，其中使用深离子注入工艺来形成掩埋电阻器，并且在形成阱区域中使用较浅的离子注入工艺。
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公开(公告)号：US07902606B2
公开(公告)日：2011-03-08
申请号：US11972811
申请日：2008-01-11
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7838 , H01L21/26586 , H01L29/0653 , H01L29/0688 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abuts the body layer and provides an electrical bias to the body layer. A top electrode and source and drain regions are formed on the body layer. The thickness of the body layer is selected to allow full depletion of the body layer by the top electrode and a bottom electrode layer. The portion of the body layer underneath the shallow trench extends the length of a channel to enable a high voltage operation. Further, the MOSFET provides a double gate configuration and a tight control of the channel to enable a complete pinch-off of the channel and a low off-current in a compact volume.
摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）具有跟随半导体衬底的暴露表面的轮廓的主体层，并且包含浅沟槽的底表面和相邻的侧壁。 底部电极层垂直邻接体层并向身体层提供电偏压。 顶部电极和源极和漏极区域形成在主体层上。 选择体层的厚度以允许顶层电极和底电极层完全耗尽体层。 浅沟槽下面的体层的部分延伸通道的长度以实现高电压操作。 此外，MOSFET提供双栅极配置和通道的严格控制，以实现通道的完全夹断和紧凑体积中的低截止电流。
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公开(公告)号：US20100171148A1
公开(公告)日：2010-07-08
申请号：US12725792
申请日：2010-03-17
申请人： Xuefeng LIU , Robert M. RASSEL , Steven H. VOLDMAN
发明人： Xuefeng LIU , Robert M. RASSEL , Steven H. VOLDMAN
IPC分类号： H01L27/06
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/7378
摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N− well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N− well, a P+ diffusion region in contact with the N− well, and shallow trench isolation structures between the N+ and P+ diffusion regions.
摘要翻译： 一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部 。 该装置还包括连接第一和第二子集电极的连通结构和形成在第二外延层的一部分中并与第二子集电极和达到通孔结构接触的N阱。 该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区和N +和P +扩散区之间的浅沟槽隔离结构。
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