公开(公告)号：US20110156223A1

公开(公告)日：2011-06-30

申请号：US12647796

申请日：2009-12-28

申请人： Renata A. Camillo-Castillo ,  Robert J. Gauthier, JR. ,  Richard A. Phelps ,  Robert M. Rassel ,  Andreas D. Stricker

发明人： Renata A. Camillo-Castillo ,  Robert J. Gauthier, JR. ,  Richard A. Phelps ,  Robert M. Rassel ,  Andreas D. Stricker

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L29/8086 ,  H01L21/76283 ,  H01L29/66901 ,  H01L29/7846

摘要： An integrated circuit (IC) chip is provided comprising at least one trench including a stress-inducing material which imparts a stress on a channel region of a device, such as a junction gate field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). A related method is also disclosed.

摘要翻译： 提供了一种集成电路（IC）芯片，其包括至少一个沟槽，该至少一个沟槽包括在器件的沟道区域上施加应力的应力诱导材料，诸如结栅场效应晶体管（JFET）或金属氧化物 - 半导体场效应晶体管（MOSFET）。 还公开了相关方法。

公开(公告)号：US20090258464A1

公开(公告)日：2009-10-15

申请号：US12099904

申请日：2008-04-09

申请人： Renata Camillo-Castillo ,  Robert J. Gauthier, JR. ,  Richard A. Phelps ,  Andreas D. Stricker

发明人： Renata Camillo-Castillo ,  Robert J. Gauthier, JR. ,  Richard A. Phelps ,  Andreas D. Stricker

IPC分类号： H01L21/337

CPC分类号： H01L29/808 ,  H01L27/098 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/66901

摘要： Methods for manufacturing a high voltage junction field effect transistor. The method includes forming an opening extending from a top surface of a device layer of a hybrid orientation technology (HOT) wafer through the device layer and an insulating layer to expose a portion of a bulk layer, and filling the opening with epitaxial semiconductor material having the crystalline orientation of the bulk layer. The method further includes forming first and second p-n junctions in the epitaxial semiconductor material that are arranged in depth within the epitaxial semiconductor material between the second semiconductor layer and the top surface of the first semiconductor layer.

摘要翻译： 制造高压结场效应晶体管的方法。 该方法包括从混合定向技术（HOT）晶片的器件层的顶表面延伸通过器件层和绝缘层形成开口以露出本体层的一部分，并且用具有外延半导体材料的开口填充开口，该外延半导体材料具有 本体层的晶体取向。 该方法还包括在外延半导体材料中形成在第二半导体层和第一半导体层的顶表面之间的外延半导体材料内的深度布置的第一和第二p-n结。

公开(公告)号：US20120326766A1

公开(公告)日：2012-12-27

申请号：US13168232

申请日：2011-06-24

申请人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Robert J. Gauthier, JR. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Yun Shi ,  Andreas D. Stricker

发明人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Robert J. Gauthier, JR. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Yun Shi ,  Andreas D. Stricker

IPC分类号： H03K17/72 ,  H01L29/74 ,  G06F17/50 ,  H01L21/311

CPC分类号： H01L29/7315 ,  G06F17/5063 ,  H01L27/0262 ,  H01L29/66393 ,  H01L29/7436

摘要： Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

摘要翻译： 可控硅整流器的器件结构，制造方法，操作方法和设计结构。 该方法包括以足以调节SCR的触发电流的水平对可控硅整流器（SCR）的区域施加机械应力。 装置和设计结构包括具有阳极的SCR，阴极，第一区域和与第一区域相反的导电类型的第二区域。 SCR的第一和第二区域设置在SCR的阳极和阴极之间的通电路径中。 层相对于第一区域定位在半导体衬底的顶表面上，并且被配置为在SCR的第一区域中产生一个足以调制SCR的触发电流的电平的机械应力。

公开(公告)号：US20120306014A1

公开(公告)日：2012-12-06

申请号：US13150612

申请日：2011-06-01

申请人： Renata Camillo-Castillo ,  Erik Mattias Dahlstrom ,  Robert J. Gauthier, JR. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Jed Hickory Rankin ,  Yun Shi

发明人： Renata Camillo-Castillo ,  Erik Mattias Dahlstrom ,  Robert J. Gauthier, JR. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Jed Hickory Rankin ,  Yun Shi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66492 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7843

摘要： A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.

摘要翻译： 横向扩散金属氧化物半导体场效应晶体管（LDMOS晶体管）采用增强载流子迁移率（即导通电流）的应力层，同时还保持器件的高击穿电压。 由于漂移区域的掺杂浓度的增加被最小化，因此保持高的击穿电压。 在相邻的衬底中形成阱区和漂移区。 第一浅沟槽隔离（STI）区域形成在阱区域上并与阱区域相邻，并且第二STI区域形成在漂移区域上并与漂移区域相邻。 应力层沉积在LDMOS晶体管和第二STI区域中，第二STI区域根据应力层的极性将压缩或拉伸应力传播到漂移区域。 应力层的一部分可以在栅极上去除以改变栅极下方的反转区域中的应力极性。

公开(公告)号：US20130258532A1

公开(公告)日：2013-10-03

申请号：US13431347

申请日：2012-03-27

申请人： William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Junjun Li

发明人： William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Junjun Li

IPC分类号： H01L27/06 ,  H01L21/20 ,  H01L21/33 ,  G06F17/50 ,  H01L21/8249 ,  H01L29/06 ,  H01L29/73 ,  H02H7/20 ,  H01L21/331

CPC分类号： H01L27/0262 ,  G06F17/5072 ,  H01L21/8249 ,  H01L21/845 ,  H01L27/0255 ,  H01L27/06 ,  H01L27/1211 ,  H01L29/06

摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

公开(公告)号：US20130009207A1

公开(公告)日：2013-01-10

申请号：US13614072

申请日：2012-09-13

申请人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

发明人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

IPC分类号： H01L29/74

CPC分类号： H01L29/74 ,  H01L21/823892 ,  H01L27/0262 ,  H01L27/0928 ,  H01L2924/0002 ,  H01L2924/00

摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.

摘要翻译： 使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。 垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。 也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

公开(公告)号：US20120300349A1

公开(公告)日：2012-11-29

申请号：US13115492

申请日：2011-05-25

申请人： Michel J. Abou-Khalil ,  James P. Di Sarro ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra ,  Yang Yang

发明人： Michel J. Abou-Khalil ,  James P. Di Sarro ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra ,  Yang Yang

IPC分类号： H02H9/00 ,  G06F17/50

CPC分类号： H02H9/046 ,  G06F17/5063 ,  H01L27/0285

摘要： Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.

摘要翻译： 用于将场效应晶体管的栅极和栅极电介质与静电放电（ESD）隔离的保护电路，设计结构和方法。 保护场效应晶体管位于受保护的场效应晶体管和电压轨之间。 在正常工作条件下，保护场效应晶体管饱和，使受保护的场效应晶体管耦合到电压轨。 保护场效应晶体管可以在芯片无电源时响应于ESD事件而被驱动成截止状态，这增加了受保护的场效应晶体管的栅极与电压轨之间的ESD电流路径的串联电阻。 保护场效应晶体管两端的电压降可以降低受保护的场效应晶体管的栅极电介质上的ESD应力。 或者，现有的场效应晶体管的栅极和源极被选择性地耦合到提供ESD隔离到受保护的场效应晶体管。

公开(公告)号：US20110185332A1

公开(公告)日：2011-07-28

申请号：US12695494

申请日：2010-01-28

申请人： Robert J. Gauthier, JR. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

发明人： Robert J. Gauthier, JR. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.

摘要翻译： 提供了一种用于模拟电路的方法，装置和程序产品。 电路的多个元件由包括通过/不合格标准的器件模型表示。 在硬件实现的处理器上执行电路仿真程序，其中电路仿真程序被配置为响应于所应用的参数从设备模型获得仿真结果。 电路仿真程序基于设备模型的通过/不合格标准来识别电路的多个元件中的一个或多个元件的故障。 电路仿真程序还被配置为在模拟响应于所应用的参数识别的多个元件中的一个或多个元件期间输出故障。

公开(公告)号：US20100230732A1

公开(公告)日：2010-09-16

申请号：US12547529

申请日：2009-08-26

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  WiIliam R. Tonti ,  Yun Shi

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  WiIliam R. Tonti ,  Yun Shi

IPC分类号： H01L29/772 ,  H01L21/336 ,  H01L21/30

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.

摘要翻译： 一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。 门通过气隙与身体的至少一部分分离。 气隙也在第一平面。

公开(公告)号：US20100096536A1

公开(公告)日：2010-04-22

申请号：US12646292

申请日：2009-12-23

申请人： Wagdi W. Abadeer ,  James W. Adkisson ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Michael J. Hauser ,  Jed H. Rankin ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  James W. Adkisson ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Michael J. Hauser ,  Jed H. Rankin ,  William R. Tonti

IPC分类号： G01J1/44

CPC分类号： H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad one the packaged chip is placed in system. No additional pins on the package are necessary.

摘要翻译： 公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。 本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。 此外，为了将ESD保护装置与输入板断开，将封装的芯片放置在系统中。 不需要额外的引脚。