公开(公告)号：US20240421176A1

公开(公告)日：2024-12-19

申请号：US18734573

申请日：2024-06-05

Applicant: STMicroelectronics International N.V.

Inventor： Florian Perminjat ,  Vincent Beix ,  Yandong Mao ,  Karine Saxod

IPC: H01L27/146

Abstract: An optical package comprising a support substrate including first electrical contacts, a cap fixed to the support substrate by adhesive and comprising second electrical contacts connected to the first electrical contacts by a soldering material, a separation structure disposed between the soldering material and the adhesive

公开(公告)号：US20240419525A1

公开(公告)日：2024-12-19

申请号：US18678878

申请日：2024-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Mohamed Ali Moussa ,  Francois De Rochebouet

IPC: G06F11/07 ,  G06F17/16

Abstract: A method implemented by computer for generating a model for anomaly detection in a system includes obtaining a learning data matrix corresponding to a normal operation of the system, decomposing the learning data matrix into singular values of the matrix of learning data, calculating a new base, defining a maximum Mahalanobis distance threshold representing a limit of the normal operation of the system, and defining an anomaly detection model from the new base and from the maximum Mahalanobis distance threshold.

公开(公告)号：US12170120B2

公开(公告)日：2024-12-17

申请号：US18227545

申请日：2023-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Hitesh Chawla ,  Tanuj Kumar ,  Bhupender Singh ,  Harsh Rawat ,  Kedar Janardan Dhori ,  Manuj Ayodhyawasi ,  Nitin Chawla ,  Promod Kumar

IPC: G11C29/00 ,  G11C29/12 ,  G11C29/36

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

公开(公告)号：US20240413178A1

公开(公告)日：2024-12-12

申请号：US18674220

申请日：2024-05-24

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Rita KUO

IPC: H01L27/146 ,  H01L23/00

Abstract: A glassless wafer-level optical sensor semiconductor package is provided. A method of manufacturing a glassless wafer-level optical sensor package of an example includes: forming one or more dams at least partially surrounding one or more optical sensors on a wafer; supporting the wafer on a carrier substrate via the one or more dams; forming a wafer-level optical sensor integrated circuit for each of the one or more optical sensors on the wafer by: performing a through-silicon via process on the wafer; forming an isolation layer on the wafer; and performing a passivation operation on the wafer; removing the wafer from the carrier substrate; and singulating each wafer-level optical sensor integrated circuit.

公开(公告)号：US12165680B1

公开(公告)日：2024-12-10

申请号：US18538724

申请日：2023-12-13

Applicant: STMicroelectronics International N.V.

Inventor： Enrico Sentieri ,  Paolo Pulici ,  Enrico Mammei ,  Michele Bartolini ,  Matteo Tonelli

IPC: G11B5/60

Abstract: A method for determining a fly height includes measuring a first differential voltage between a first head of a disk drive and a reference voltage with a first front end circuit, converting the first differential voltage to a first analog current signal with the first front end circuit, and converting the first analog current signal to a second differential voltage with a first back end circuit. The first front end circuit is coupled with the first head. The first back end circuit is coupled with the first front end circuit. The method further includes determining a first capacitance between the first head and a first disk of the disk drive based on the second differential voltage and determining the fly height between the first head and the first disk using the first capacitance.

公开(公告)号：US12164002B2

公开(公告)日：2024-12-10

申请号：US18066783

申请日：2022-12-15

Applicant: STMicroelectronics International N.V.

Inventor： John Kevin Moore ,  Gavin Stuart Ball

IPC: G01R31/317 ,  G04F10/00

Abstract: A time-to-digital converter (TDC) circuit with self-testing function includes: a D flip-flop, where an input terminal of the D flip-flop is configured to be coupled to a data signal, and a clock terminal of the D flip-flop is configured to be coupled to a clock signal; and an AND gate, where a first input terminal of the AND gate is configured to be coupled to an enable signal of the TDC circuit, a second input terminal of the AND gate is configured to be coupled to a test signal, and an output terminal of the AND gate is coupled to a control terminal of the D flip-flop.

公开(公告)号：US20240405798A1

公开(公告)日：2024-12-05

申请号：US18651120

申请日：2024-04-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Riccardo CONDORELLI ,  Antonino MONDELLO ,  Michele Alessandro CARRANO ,  Salvatore COSTA ,  Michele BOTTARO ,  Pascal FABRE ,  Philippe BOLLARD ,  Felice Alberto TORRISI

IPC: H04B1/7183 ,  H04L7/033

Abstract: Method of operating a radio communication system during a stand-by time interval in a stand-by state. The method comprises: applying clock division processing to a reference clock signal and producing a divided clock signal; applying PLL processing to the divided clock signal producing a PLL clock signal; receiving at least one input signal; when the input signal has a first logic value, interrupting applying PLL processing to the divided clock signal and enabling counting clock signal edges of the divided clock signal; when said counting clock signal edges reaches a first target count value, restarting applying PLL processing; continuing counting clock signal edges until reaching a second target count value; when said counting reaches the second target count value, issuing and sampling an end-count signal based on the PLL clock signal, producing a timing clock signal as a result and providing the timing clock signal to a user circuit.

公开(公告)号：US20240405670A1

公开(公告)日：2024-12-05

申请号：US18203299

申请日：2023-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Yannick HAGUE ,  Romain LAUNOIS ,  Guillaume THIENNOT

IPC: H02M1/42 ,  H02M1/00 ,  H02M1/08

Abstract: A bidirectional PFC system includes a high-frequency branch with a first transistor connected between an IO node and a high-frequency tap, and a second transistor connected between the high-frequency tap and a reference node, and a low-frequency branch with a first thyristor connected between the IO node and a low-frequency tap, and a second thyristor connected between the low-frequency tap and the reference node. An inductor is connected between the first node and the high-frequency tap. A first capacitor is connected between the first node and the low-frequency tap. The first node and the low-frequency tap are coupled to input terminals. A control circuit generates first and second gate drive signals for the transistors so as to modify an AC signal at the input terminals such that the AC current falls below a holding current of the second thyristor prior to zero crossing of the AC voltage.

公开(公告)号：US20240404596A1

公开(公告)日：2024-12-05

申请号：US18676719

申请日：2024-05-29

Applicant: STMicroelectronics International N.V.

Inventor： Antonino CONTE ,  Francesco LA ROSA

IPC: G11C13/00

Abstract: First, second input terminals of a sense amplifier are coupled to first, second memory sensing nodes. A first input transistor has a channel arranged between a first comparator input and a first comparator output, and a control terminal at a bias node. A second input transistor has a channel arranged between a second comparator input and a second comparator output, and a control terminal at a bias node. The first and second comparator inputs are selectively couplable to each other, in response to compensation signal assertion, or to the first and second input terminals, in response to compensation signal de-assertion. The bias node is selectively couplable to a comparator biasing node in response to bias enable assertion, or is floating in response to the bias enable de-assertion. A sensing circuit produces a read signal as a function of a difference between first, second currents at the comparator outputs.

公开(公告)号：US20240403602A1

公开(公告)日：2024-12-05

申请号：US18204069

申请日：2023-05-31

Applicant: STMicroelectronics International N.V.

Inventor： Tommaso MILANESE ,  Edoardo Charbon ,  Brent Hearn

IPC: G06N3/0442 ,  G06F17/16

Abstract: Systems, apparatuses, methods, and computer programming products for machine learning with a LSTM accelerator are provided. The LSTM accelerator may comprise a finite state machine (FSM) configured with a plurality of states comprising a machine learning algorithm; a weight memory configured to at least store a plurality of weights and a plurality of biases; one or more activation registers; a hidden state memory; and a plurality of processing elements. The LSTM accelerator may apply the machine learning algorithm of the FSM by performing a plurality of operations with the plurality of processing elements including one or more matrix-vector multiplication operations, vector-vector multiplication operations, vector-vector addition operations, and non-linear activation operations.