中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

78 records (took 0.026 seconds)

    Method for making ultrahigh speed bipolar transistor
    41.
    发明授权
    Method for making ultrahigh speed bipolar transistor 失效
    制造超高速双极晶体管的方法

    公开(公告)号：US5773349A

    公开(公告)日：1998-06-30

    申请号：US664861

    申请日：1996-06-17

    Applicant: Seog-Heon Ham

    Inventor： Seog-Heon Ham

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/70 ,  H01L29/732

    CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/7322

    Abstract: An ultrahigh speed bipolar transistor has a base region which is formed from a P.sup.+ base polysilicon sidewall using a self-alignment method, and a base junction window which is formed in order to minimize the collector-base junction capacity. In the method for fabricating this transistor, an insulation layer of oxide silicon or nitrogen silicon is formed under the base polysilicon layer. Accordingly, impurities from the base polysilicon layer do not diffuse into the epitaxial layer during the diffusion process. Instead, the extrinsic base region is formed by the diffusion of impurities from the polysilicon sidewall which is connected to the base polysilicon layer. Therefore the length of the entire base region is shortened. Furthermore, the junction area between the collector region is also lowered. Thus, the collector-base junction capacity is decreased and a higher operating speed is obtained.

    Abstract translation: 超高速双极晶体管具有使用自对准方法由P +基底多晶硅侧壁形成的基极区域和形成为使集电极 - 基极结电容最小化的基极结窗口。 在制造该晶体管的方法中，在基底多晶硅层下方形成氧化硅或氮硅的绝缘层。 因此，在扩散过程中，来自基底多晶硅层的杂质不扩散到外延层中。 相反，外部基极区域通过杂质从连接到基底多晶硅层的多晶硅侧壁扩散而形成。 因此，整个基区的长度缩短。 此外，集电区域之间的接合面积也降低。 因此，集电极 - 基极结的容量降低并且获得更高的工作速度。

    Method for manufacturing ultra-high speed bipolar transistor
    42.
    发明授权
    Method for manufacturing ultra-high speed bipolar transistor 失效
    制造超高速双极晶体管的方法

    公开(公告)号：US5654211A

    公开(公告)日：1997-08-05

    申请号：US664823

    申请日：1996-06-17

    Applicant: Seog Heon Ham

    Inventor： Seog Heon Ham

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732 ,  H01L21/265

    CPC classification number: H01L29/66272 ,  H01L29/7322

    Abstract: A method of producing the bipolar transistor includes forming an aperture through a triple layer over an active region of an epitaxial layer, then forming a shallow polysilicon film at the bottom of the aperture. An intrinsic base region is formed by segregating a conductive impurity to the epitaxial layer by thermally oxidizing the polysilicon film. Then an extrinsic base region is formed by diffusing impurities into the epitaxial layer from a polysilicon sidewall formed on the aperture. In the transistor fabricated according to this method, an insulation layer of oxide silicon or nitrogen silicon is formed under the base polysilicon layer. Accordingly, impurities from the base polysilicon layer do not diffuse into the epitaxial layer during the diffusion process. Instead, the extrinsic base region is formed by the diffusion of impurities from the polysilicon sidewall which is connected to the base polysilicon layer. Therefore the length of the entire base region is shortened. Furthermore, by forming the intrinsic base region by thermally oxidizing the shallow polysilicon film, the base width and the transmission time are reduced, thus leading to a higher performance speed of the element.

    Abstract translation: 制造双极晶体管的方法包括在外延层的有源区上通过三层形成孔，然后在孔的底部形成浅多晶硅膜。 通过热氧化多晶硅膜将导电杂质分离到外延层上形成本征基极区。 然后通过在孔径上形成的多晶硅侧壁将杂质扩散到外延层中形成非本征基区。 在根据该方法制造的晶体管中，在基底多晶硅层下形成氧化硅或氮硅的绝缘层。 因此，在扩散过程中，来自基底多晶硅层的杂质不扩散到外延层中。 相反，外部基极区域通过杂质从连接到基底多晶硅层的多晶硅侧壁扩散而形成。 因此，整个基区的长度缩短。 此外，通过热氧化浅多晶硅膜形成本征基极区域，减小基极宽度和透射时间，从而导致元件的更高的性能。

    Correlated double sampling circuit and image sensor including the same
    47.
    发明授权
    Correlated double sampling circuit and image sensor including the same 有权
    相关的双采样电路和图像传感器包括相同的

    公开(公告)号：US08638383B2

    公开(公告)日：2014-01-28

    申请号：US13171958

    申请日：2011-06-29

    Applicant: Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

    Inventor： Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

    IPC: H04N3/14 ,  H04N5/335

    CPC classification number: H03M3/342 ,  H04N5/378

    Abstract: A correlated double sampling circuit includes a delta-sigma modulator, a selection circuit, and an accumulation circuit. The delta-sigma modulator is configured to receive an input signal, delta-sigma modulate the input signal, and output a modulation signal. The selection circuit is configured to invert the modulation signal and selectively output one of the modulation signal and an inverted modulation signal in response to a selection signal corresponding to an operation phase. The accumulation circuit is configured to generate a first accumulation result by performing an accumulation process on one of the modulation signal and the inverted modulation signal in a first operation phase, and generate a second accumulation result by performing the accumulation process on the first accumulation result and the other one of the modulation signal and the inverted modulation signal in a second operation phase.

    Abstract translation: 相关双采样电路包括Δ-Σ调制器，选择电路和累积电路。 Δ-Σ调制器被配置为接收输入信号，Δ-Σ调制输入信号，并输出调制信号。 选择电路被配置为响应于对应于操作阶段的选择信号，反转调制信号并选择性地输出调制信号和反相调制信号中的一个。 累积电路被配置为通过在第一操作阶段中对调制信号和反相调制信号之一执行累加处理来产生第一累加结果，并且通过对第一累积结果执行累积处理来生成第二累加结果，以及 在第二操作阶段中的另一个调制信号和反相调制信号。

    Analog-to-digital converter for controlling gain by changing a system parameter, image sensor including the analog-to-digital converter and method of operating the analog-to-digital converter
    48.
    发明授权
    Analog-to-digital converter for controlling gain by changing a system parameter, image sensor including the analog-to-digital converter and method of operating the analog-to-digital converter 有权
    用于通过改变系统参数来控制增益的模数转换器，包括模数转换器的图像传感器和操作模数转换器的方法

    公开(公告)号：US08605176B2

    公开(公告)日：2013-12-10

    申请号：US12879684

    申请日：2010-09-10

    Applicant: Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

    Inventor： Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

    IPC: H04N3/14

    CPC classification number: H04N5/378 ,  H03M3/48

    Abstract: Example embodiments are directed to an analog-to-digital converter (ADC) that controls a gain by changing a system parameter, an image sensor including the ADC and a method of operating the ADC. The ADC includes a sigma-delta modulator which receives an input signal and a clock signal and sigma-delta modulates the input signal into a digital output signal based on the clock signal and an accumulation unit which accumulates the digital output signal at each cycle of the clock signal according to an analog-to-digital conversion time and outputs an accumulation result. A system parameter is varied during the analog-to-digital conversion time to control a gain of the ADC. The method of operating the analog-to-digital converter includes sigma-delta modulating an input signal into a digital output signal in response to a clock signal input to the ADC; and accumulating the digital output signal at each cycle of the input clock signal according to an analog-to-digital conversion time and outputting an accumulation result.

    Abstract translation: 示例性实施例涉及通过改变系统参数来控制增益的模数转换器（ADC），包括ADC的图像传感器和操作ADC的方法。 ADC包括Σ-Δ调制器，其接收输入信号和时钟信号，并且Σ-Δ基于时钟信号将输入信号调制成数字输出信号;以及累积单元，其在每个周期的每个周期累积数字输出信号 时钟信号，并输出累积结果。 在模数转换时间期间，系统参数会发生变化，以控制ADC的增益。 操作模数转换器的方法包括响应于输入到ADC的时钟信号而将输入信号Σ-Δ调制成数字输出信号; 并且根据模数转换时间在输入时钟信号的每个周期累加数字输出信号，并输出累加结果。

    Image sensors and image processing systems
    49.
    发明授权
    Image sensors and image processing systems 有权
    图像传感器和图像处理系统

    公开(公告)号：US08593319B2

    公开(公告)日：2013-11-26

    申请号：US13611451

    申请日：2012-09-12

    Applicant: Min-Ho Kwon ,  Seog-Heon Ham ,  Jeong-Jin Roh ,  Jae-Jin Yeo ,  Yong-Suk Choi ,  Gun-Hee Han

    Inventor： Min-Ho Kwon ,  Seog-Heon Ham ,  Jeong-Jin Roh ,  Jae-Jin Yeo ,  Yong-Suk Choi ,  Gun-Hee Han

    IPC: H03M3/00

    CPC classification number: H04N5/3698 ,  H03M3/324 ,  H03M3/368 ,  H03M3/43 ,  H03M3/452 ,  H04N5/374 ,  H04N5/378

    Abstract: An image sensor includes a delta-sigma analog-to-digital converter (ADC) including a delta-sigma modulator (DSM) and a voltage adjusting circuit. The DSM is configured to perform delta-sigma modulation on an analog signal from a unit pixel. The delta-sigma ADC is configured to convert the analog signal to a digital signal. The voltage adjusting circuit includes a replica inverter having a same configuration as at least one inverter included in the DSM. The voltage adjusting circuit is configured to adjust a power supply voltage and an input voltage provided to the at least one inverter based on a current flowing in the replica inverter.

    Abstract translation: 图像传感器包括包括Δ-Σ调制器（DSM）和电压调节电路的Δ-Σ模数转换器（ADC）。 DSM被配置为对来自单位像素的模拟信号执行Δ-Σ调制。 Δ-ΣADC配置为将模拟信号转换为数字信号。 电压调整电路包括具有与DSM中包括的至少一个反相器相同配置的复制反相器。 电压调整电路被配置为基于在复制逆变器中流动的电流来调整提供给至少一个逆变器的电源电压和输入电压。

Patent Agency Ranking