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    Image sensor for high-speed data readout
    2.
    发明授权
    Image sensor for high-speed data readout 有权
    用于高速数据读出的图像传感器

    公开(公告)号：US08159589B2

    公开(公告)日：2012-04-17

    申请号：US12427214

    申请日：2009-04-21

    Applicant: Seung Hyun Lim ,  Gun Hee Han ,  Seog Heon Ham

    Inventor： Seung Hyun Lim ,  Gun Hee Han ,  Seog Heon Ham

    IPC: H04N5/335

    CPC classification number: H04N5/37455 ,  G11C7/16

    Abstract: An image sensor for high-speed data readout is provided. The image sensor includes a line memory block temporarily storing a digital signal in unit of lines which is generated based on an analog signal output from a pixel array. The line memory block includes a plurality of line memories, a plurality of data line pairs respectively connecting the line memories to a sense amplifying unit, and a plurality of data line prechargers each including at least two precharge units separately connected with a corresponding one of the data line pairs to precharge the corresponding data line pair with a predetermined precharge voltage. Accordingly, the image sensor performs high-speed digital signal readout based on precharge operation of the data line prechargers.

    Abstract translation: 提供了用于高速数据读出的图像传感器。 该图像传感器包括一个行存储块，其临时存储基于从像素阵列输出的模拟信号产生的行单位的数字信号。 行存储块包括多个行存储器，分别将行存储器连接到读出放大单元的多个数据线对，以及多个数据线预充电器，每个数据线预充电器包括分别与相应的一个 数据线对以预定的预充电电压对相应的数据线对进行预充电。 因此，图像传感器基于数据线预充电器的预充电操作来执行高速数字信号读出。

    Analog digital converters and image sensors including the same
    3.
    发明授权
    Analog digital converters and image sensors including the same 失效
    模拟数字转换器和图像传感器包括相同的

    公开(公告)号：US08094058B2

    公开(公告)日：2012-01-10

    申请号：US12654856

    申请日：2010-01-06

    Applicant: Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

    Inventor： Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

    IPC: H03M1/50

    CPC classification number: H03M3/39 ,  H03M3/462

    Abstract: The analog-digital converter (ADC) includes a modulator and a digital integrator. The modulator is configured to modulate an input signal and output a modulated signal. The digital integrator includes a plurality of accumulators serially connected to one another. The digital integrator is configured to integrate the modulated signal to output an integration result.

    Abstract translation: 模拟数字转换器（ADC）包括调制器和数字积分器。 调制器被配置为调制输入信号并输出​​调制信号。 数字积分器包括彼此串联连接的多个累加器。 数字积分器被配置为集成调制信号以输出积分结果。

    ANALOG-TO-DIGITAL CONVERTER AND IMAGE SENSOR INCLUDING SAME
    6.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER AND IMAGE SENSOR INCLUDING SAME 有权
    模拟数字转换器和图像传感器，包括它们

    公开(公告)号：US20120097840A1

    公开(公告)日：2012-04-26

    申请号：US13276927

    申请日：2011-10-19

    Applicant: Jin Woo Kim ,  Seog Heon Ham ,  Kyung-Min Kim ,  Yong Lim

    Inventor： Jin Woo Kim ,  Seog Heon Ham ,  Kyung-Min Kim ,  Yong Lim

    IPC: H03M1/34 ,  H01L27/146 ,  H03M1/12

    CPC classification number: H03M1/002 ,  H03M1/123 ,  H03M1/56 ,  H04N5/37213 ,  H04N5/378

    Abstract: An analog-to-digital converter (ADC) within an image sensor includes a comparator comparing a ramp signal with an image signal, and a counter generating a count result in response to the comparison by counting a clock during a counting interval. The ADC determines whether a first counting interval for the counter is less than a reference interval, and if the first counting interval is less than the reference interval the counting interval is a first counting interval, else the counting interval is a second counting interval.

    Abstract translation: 图像传感器内的模数转换器（ADC）包括将斜坡信号与图像信号进行比较的比较器，以及通过在计数间隔期间对时钟进行计数来产生响应于比较的计数结果的计数器。 ADC确定计数器的第一计数间隔是否小于参考间隔，并且如果第一计数间隔小于参考间隔，则计数间隔是第一计数间隔，否则计数间隔是第二计数间隔。

    CORRELATED DOUBLE SAMPLING CIRCUIT AND IMAGE SENSOR INCLUDING THE SAME
    7.
    发明申请
    CORRELATED DOUBLE SAMPLING CIRCUIT AND IMAGE SENSOR INCLUDING THE SAME 有权
    相关的双重采样电路和包括其的图像传感器

    公开(公告)号：US20120002093A1

    公开(公告)日：2012-01-05

    申请号：US13171958

    申请日：2011-06-29

    Applicant: Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

    Inventor： Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

    IPC: H04N5/335 ,  H03M3/00

    CPC classification number: H03M3/342 ,  H04N5/378

    Abstract: A correlated double sampling circuit includes a delta-sigma modulator, a selection circuit, and an accumulation circuit. The delta-sigma modulator is configured to receive an input signal, delta-sigma modulate the input signal, and output a modulation signal. The selection circuit is configured to invert the modulation signal and selectively output one of the modulation signal and an inverted modulation signal in response to a selection signal corresponding to an operation phase. The accumulation circuit is configured to generate a first accumulation result by performing an accumulation process on one of the modulation signal and the inverted modulation signal in a first operation phase, and generate a second accumulation result by performing the accumulation process on the first accumulation result and the other one of the modulation signal and the inverted modulation signal in a second operation phase.

    Abstract translation: 相关双采样电路包括Δ-Σ调制器，选择电路和累积电路。 Δ-Σ调制器被配置为接收输入信号，Δ-Σ调制输入信号，并输出调制信号。 选择电路被配置为响应于对应于操作阶段的选择信号，反转调制信号并选择性地输出调制信号和反相调制信号中的一个。 累积电路被配置为通过在第一操作阶段中对调制信号和反相调制信号之一执行累加处理来产生第一累加结果，并且通过对第一累积结果执行累积处理来生成第二累加结果，以及 在第二操作阶段中的另一个调制信号和反相调制信号。

    Analog-to-digital converters, and image sensors and image processing devices having the same
    9.
    发明申请
    Analog-to-digital converters, and image sensors and image processing devices having the same 有权
    模拟数字转换器，以及具有该转换器的图像传感器和图像处理装置

    公开(公告)号：US20110050473A1

    公开(公告)日：2011-03-03

    申请号：US12801062

    申请日：2010-05-20

    Applicant: Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

    Inventor： Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

    IPC: H03M3/00

    CPC classification number: H03M3/356 ,  H03M3/458

    Abstract: An analog-digital converter (ADC) includes a correlated double sampling (CDS) circuit configured to perform CDS on each of a reset signal and an image signal output from a pixel to generate a correlated double sampled reset signal and a correlated double sampled image signal, respectively. A delta sigma (ΔΣ) ADC, also included in the ADC, is configured to output a difference between a first digital code that is generated by performing ΔΣ analog-digital conversion on the correlated double sampled reset signal and a second digital code that is generated by performing ΔΣ analog-digital conversion on the correlated double sampled image signal.

    Abstract translation: 模拟数字转换器（ADC）包括相关双采样（CDS）电路，其被配置为在复位信号和从像素输出的图像信号中的每一个上执行CDS，以产生相关的双采样复位信号和相关的双采样图像信号 ， 分别。 还包括在ADC中的Δ西格玛（＆Dgr;＆Sgr）ADC被配置为输出通过执行＆Dgr＆amp; Sgr生成的第一数字代码之间的差异。 对相关的双重采样复位信号进行模拟数字转换和通过执行＆Dgr＆amp; 对相关双采样图像信号进行模数转换。

    Sigma-delta analog-to-digital converter and solid-state image pickup device
    10.
    发明申请
    Sigma-delta analog-to-digital converter and solid-state image pickup device 有权
    Sigma-delta模数转换器和固态图像拾取器件

    公开(公告)号：US20090289823A1

    公开(公告)日：2009-11-26

    申请号：US12453845

    申请日：2009-05-26

    Applicant: Youngcheol Chae ,  In Hee Lee ,  Gunhee Han ,  Seog Heon Ham

    Inventor： Youngcheol Chae ,  In Hee Lee ,  Gunhee Han ,  Seog Heon Ham

    IPC: H03M3/00

    CPC classification number: H03M3/384 ,  H03M3/424

    Abstract: A sigma-delta analog-to-digital converter may include a sigma-delta modulator and a decimation filter. The sigma-delta modulator may convert a first analog input signal into a first bit stream having a first pattern using sigma-delta modulation and convert a second analog input signal into a second bit stream having a second pattern using the sigma-delta modulation. The decimation filter may integrate the number of bits having a particular value in the first bit stream, output a first digital value, calculate a bitwise complement value of the first digital value, integrate the number of bits having the particular value in the second bit stream with the bitwise complement value of the first digital value as an initial value of a second digital value, and output the second digital value.

    Abstract translation: Σ-Δ模数转换器可以包括Σ-Δ调制器和抽取滤波器。 Σ-Δ调制器可以使用Σ-Δ调制将第一模拟输入信号转换成具有第一模式的第一比特流，并且使用Σ-Δ调制将第二模拟输入信号转换成具有第二模式的第二比特流。 抽取滤波器可以将具有特定值的比特数量集成在第一比特流中，输出第一数字值，计算第一数字值的按位补码，将具有特定值的比特数集成在第二比特流中 以第一数字值的按位补码作为第二数字值的初始值，并输出第二数字值。

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