公开(公告)号：US20140293469A1

公开(公告)日：2014-10-02

申请号：US13850297

申请日：2013-03-26

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Cheng-Hung YU

IPC: G02B5/20 ,  G03F7/00

CPC classification number: G02B5/201 ,  G03F7/0007

Abstract: A method for fabricating a color filter layer, which is applied to an integrated circuit manufacturing process, includes the following steps. Firstly, a substrate is provided, and a groove structure is formed on the substrate. The groove structure includes a plurality of positive photoresist patterns and a plurality of trenches. Then, a first group of color filter patterns is formed in the trenches. The plurality of positive photoresist patterns is removed, so that a portion of a top surface of the substrate is exposed. Then, a second group of color filter patterns is formed on the exposed top surface of the substrate.

Abstract translation: 应用于集成电路制造工艺的制造滤色器层的方法包括以下步骤。 首先，设置基板，在基板上形成槽结构。 凹槽结构包括多个正光致抗蚀剂图案和多个沟槽。 然后，在沟槽中形成第一组滤色器图案。 去除多个正光致抗蚀剂图案，使得基板的顶表面的一部分被暴露。 然后，在曝光的基板的顶表面上形成第二组滤色器图案。

公开(公告)号：US08828827B2

公开(公告)日：2014-09-09

申请号：US14010491

申请日：2013-08-26

Applicant: United Microelectronics Corporation

Inventor： Chun-Yao Lee ,  Chin-Lung Chen ,  Wei-Chun Chang ,  Hung-Te Lin ,  Han-Min Huang

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66477 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

Abstract: A manufacturing method of an anti punch-through leakage current MOS transistor is provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.

Abstract translation: 提供一种抗穿通漏电流MOS晶体管的制造方法。 在第二类型的衬底中形成高电压深第一类型阱区和第一类型掺杂区。 具有掺杂剂注入口的掩模形成在第二类型衬底上。 通过在掺杂剂注入口中注入第一种类型的掺杂剂形成抗穿透漏电流结构。 高压深度第一类型阱区域的第一种掺杂剂的掺杂浓度小于抗穿透漏电流结构的掺杂浓度，并且大于高电压深度第一类型阱区域的掺杂浓度。 通过在掺杂剂注入口中注入第二种掺杂剂形成第二类型体。 栅极结构形成在第二类型基板上。

公开(公告)号：US08809163B2

公开(公告)日：2014-08-19

申请号：US14095988

申请日：2013-12-03

Applicant: United Microelectronics Corporation

Inventor： Kuan-Ling Liu ,  Shih-Yuan Ueng

IPC: H01L21/76 ,  H01L21/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/66666 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/4236 ,  H01L29/6634 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L2924/00 ,  H01L2924/10253

Abstract: A fabricating method of a trench-gate metal oxide semiconductor device is provided. The fabricating method includes the steps of defining a first zone and a second zone in a substrate, forming at least one first trench in the second zone, forming a dielectric layer on the first zone and the second zone, filling the dielectric layer in the first trench, performing an etching process to form at least one second trench in the first zone by using the dielectric layer as an etching mask, forming a first gate dielectric layer on a sidewall of the second trench, and filling a conducting material layer into the second trench, thereby forming a first gate electrode.

Abstract translation: 提供了一种沟槽栅极金属氧化物半导体器件的制造方法。 制造方法包括以下步骤：在衬底中限定第一区域和第二区域，在第二区域中形成至少一个第一沟槽，在第一区域和第二区域上形成介电层，在第一区域和第二区域中填充介电层 沟槽，通过使用介电层作为蚀刻掩模，在第一区域中形成至少一个第二沟槽，在第二沟槽的侧壁上形成第一栅介质层，并将导电材料层填充到第二沟槽中， 从而形成第一栅电极。

公开(公告)号：US20140199819A1

公开(公告)日：2014-07-17

申请号：US13742359

申请日：2013-01-16

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Pao-Chu CHANG

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L21/311 ,  H01L21/31144 ,  H01L23/5223 ,  H01L28/60 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a capacitor structure includes the following steps. Firstly, a substrate is provided. A first conductive layer, a first insulation layer, a second conductive layer and a second insulation layer are sequentially formed over the substrate. A hard mask material layer is formed on the second insulation layer. Then, the hard mask material layer is defined with a photo resist pattern, so that a hard mask is formed. After the photo resist pattern is removed, the second conductive layer is defined with the hard mask, so that a first electrode of the capacitor structure is formed.

Abstract translation: 制造电容器结构的方法包括以下步骤。 首先，提供基板。 在衬底上顺序地形成第一导电层，第一绝缘层，第二导电层和第二绝缘层。 硬掩模材料层形成在第二绝缘层上。 然后，用光致抗蚀剂图案限定硬掩模材料层，从而形成硬掩模。 在去除光致抗蚀剂图案之后，用硬掩模限定第二导电层，从而形成电容器结构的第一电极。

公开(公告)号：US20140094013A1

公开(公告)日：2014-04-03

申请号：US14095988

申请日：2013-12-03

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kuan-Ling LIU ,  Shih-Yuan Ueng

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/4236 ,  H01L29/6634 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L2924/00 ,  H01L2924/10253

Abstract: A fabricating method of a trench-gate metal oxide semiconductor device is provided. The fabricating method includes the steps of defining a first zone and a second zone in a substrate, forming at least one first trench in the second zone, forming a dielectric layer on the first zone and the second zone, filling the dielectric layer in the first trench, performing an etching process to form at least one second trench in the first zone by using the dielectric layer as an etching mask, forming a first gate dielectric layer on a sidewall of the second trench, and filling a conducting material layer into the second trench, thereby forming a first gate electrode.

Abstract translation: 提供了一种沟槽栅极金属氧化物半导体器件的制造方法。 制造方法包括以下步骤：在衬底中限定第一区域和第二区域，在第二区域中形成至少一个第一沟槽，在第一区域和第二区域上形成介电层，在第一区域和第二区域中填充介电层 沟槽，通过使用介电层作为蚀刻掩模，在第一区域中形成至少一个第二沟槽，在第二沟槽的侧壁上形成第一栅介质层，并将导电材料层填充到第二沟槽中， 从而形成第一栅电极。

公开(公告)号：US20140073109A1

公开(公告)日：2014-03-13

申请号：US14071664

申请日：2013-11-05

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Liang-An Huang ,  Yu-Chun Huang ,  Chin-Fu Lin ,  Yu-Ciao Lin ,  Yu-Chieh Lin ,  Hsin-Liang Liu ,  Chun-Hung Cheng ,  Yuan-Cheng Yang ,  Yau-Kae Sheu

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76232

Abstract: A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.

Abstract translation: 浅沟槽隔离结构的制造方法包括以下步骤。 首先，提供衬底，其中在衬底中限定高电压器件区域。 然后，执行第一蚀刻工艺以部分地去除衬底，从而在高压器件区域中形成初步浅沟槽。 然后，进行第二蚀刻处理以进一步去除对应于初步浅沟槽的衬底，从而在高电压器件区域中形成第一浅沟槽。 之后，在第一浅沟槽中填充电介质材料，从而形成第一浅沟槽隔离结构。

公开(公告)号：US08643521B1

公开(公告)日：2014-02-04

申请号：US13688158

申请日：2012-11-28

Applicant: United Microelectronics Corporation

Inventor： Hsueh-Chen Cheng ,  Wen-Hong Hsu ,  Po-Hua Chen ,  Yu-Yee Liow

IPC: H03M1/00

CPC classification number: H03M1/0818 ,  H03M1/742

Abstract: A DAC has at least one bit current-steering circuit. In the DAC, the current-steering circuit has a current source circuit, a switch, a feedback circuit, and an amplifier circuit. The current source circuit is disposed for outputting a bias current to the switch and coupled to the amplifier circuit. The switch has a first input/output terminal coupled to output an analog signal, a control terminal coupled to the feedback circuit, and a second input/output terminal for receiving the bias current, so that the first switch determines whether the first and the second input/output terminals are conducted according to a status of the control terminal.

Abstract translation: DAC具有至少一个位电流转向电路。 在DAC中，电流导向电路具有电流源电路，开关，反馈电路和放大器电路。 电流源电路被设置用于向开关输出偏置电流并耦合到放大器电路。 开关具有耦合以输出模拟信号的第一输入/输出端子，耦合到反馈电路的控制端子和用于接收偏置电流的第二输入/输出端子，使得第一开关确定第一和第二 输入/输出端子根据控制端子的状态进行。

公开(公告)号：US20130344670A1

公开(公告)日：2013-12-26

申请号：US14010491

申请日：2013-08-26

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chun-Yao LEE ,  Chin-Lung Chen ,  Wei-Chun Chang ,  Hung-Te Lin ,  Han-Min Huang

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

Abstract: A manufacturing method of an anti punch-through leakage current MOS transistor is provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.

Abstract translation: 提供一种抗穿通漏电流MOS晶体管的制造方法。 在第二类型的衬底中形成高电压深第一类型阱区和第一类型掺杂区。 具有掺杂剂注入口的掩模形成在第二类型衬底上。 通过在掺杂剂注入口中注入第一种类型的掺杂剂形成抗穿透漏电流结构。 高压深度第一类型阱区域的第一种掺杂剂的掺杂浓度小于抗穿透漏电流结构的掺杂浓度，并且大于高电压深度第一类型阱区域的掺杂浓度。 通过在掺杂剂注入口中注入第二种掺杂剂形成第二类型体。 栅极结构形成在第二类型基板上。

公开(公告)号：US20130314826A1

公开(公告)日：2013-11-28

申请号：US13956333

申请日：2013-07-31

Applicant: National Chiao Tung University ,  UNITED MICROELECTRONICS CORPORATION

Inventor： Ming-Dou Ker ,  Chun-Yu Lin ,  Chang-Tzu Wang

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0285

Abstract: An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.

Abstract translation: 提供一种适用于包括第一N沟道金属氧化物半导体（NMOS）晶体管的输入级电路的静电放电（ESD）保护电路。 ESD保护电路包括P沟道金属氧化物半导体（PMOS）晶体管和阻抗器件，其中PMOS晶体管具有耦合到第一NMOS晶体管的栅极的源极和耦合到第一NMOS晶体管的源极的漏极 并且阻抗器件耦合在PMOS晶体管的栅极和第一电源轨之间以执行初始ESD保护电路。 由PMOS晶体管和电阻器形成的ESD保护电路能够增加ESD保护电路的接通速度并防止输入级电路从CDM ESD事件发生。

公开(公告)号：US20030017688A1

公开(公告)日：2003-01-23

申请号：US09908702

申请日：2001-07-20

Applicant: United Microelectronics Corporation

Inventor： Chung-Jung Hsu ,  Chih-Hsien Huang

IPC: H01L021/3205 ,  H01L021/4763

CPC classification number: H01L21/321 ,  H01L21/32139 ,  Y10S438/952 ,  Y10S438/974

Abstract: A method for reducing hole defects in the polysilicon layer. The method at least includes the following steps. First of all, a semiconductor substrate is provided, a polysilicon layer is formed over the semiconductor substrate. Then, no hole defects bottom anti-reflective coating process is performed, wherein the no hole defect bottom anti-reflective coating process is selected from the group consisting of dehydration baking, hydrophobic solvent treatment, and steady baking. Finally, a bottom anti-reflective coating is formed over the polysilicon layer.

Abstract translation: 一种用于减少多晶硅层中的空穴缺陷的方法。 该方法至少包括以下步骤。 首先，提供半导体衬底，在半导体衬底上形成多晶硅层。 然后，不进行空穴缺陷底部防反射涂布工艺，其中无孔缺陷底部抗反射涂覆工艺选自脱水烘烤，疏水溶剂处理和稳定烘烤。 最后，在多晶硅层上形成底部抗反射涂层。