公开(公告)号：US08050089B2

公开(公告)日：2011-11-01

申请号：US12463561

申请日：2009-05-11

Applicant: Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC: G11C16/04

CPC classification number: G11C16/0408 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.

Abstract translation: 闪存器件包括多个存储器块。 多个存储块中选择的存储块包括2n页的数据。 所选存储块包括能够存储不同位数的不同类型的存储单元。

公开(公告)号：US07940578B2

公开(公告)日：2011-05-10

申请号：US12320003

申请日：2009-01-14

Applicant: Myoung-gon Kang ,  Yeong-taek Lee ,  Ki-tae Park ,  Doo-gon Kim

Inventor： Myoung-gon Kang ,  Yeong-taek Lee ,  Ki-tae Park ,  Doo-gon Kim

IPC: G11C5/14

CPC classification number: G11C16/3418 ,  G11C7/02 ,  G11C8/10 ,  G11C16/0483 ,  G11C16/3427 ,  G11C17/16 ,  G11C29/52

Abstract: A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit.

Abstract translation: 闪速存储器件包括第一和第二存储单元阵列块以及耦合到第一存储单元阵列块和第二存储单元阵列块的行解码器。 行解码器包括块解码器，耦合到第一和第二存储单元阵列块的单个高电压电平移位器，该单个高电压电平移位器被配置为向第一和第二存储单元阵列块提供高电压的块字线信号 存储器阵列块，响应于从块解码器接收的块选择信号，第一传输晶体管单元和第二传输晶体管单元。

公开(公告)号：US07940564B2

公开(公告)日：2011-05-10

申请号：US12343636

申请日：2008-12-24

Applicant: Ki-Tae Park ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Yeong-Taek Lee

IPC: G11C16/06 ,  G11C5/02 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C16/0483 ,  G11C5/02 ,  G11C5/025 ,  G11C8/14 ,  G11C8/18 ,  H01L21/8221 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551

Abstract: Disclosed is a 3D memory device including a first plane having a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats sharing a bit line, and a second plane having a second mat formed on the first layer and a fourth mat formed on the second layer. The second and fourth mats share a bit line. Each one of the first through fourth mats includes a plurality of blocks and a block associated with the first plane is simultaneously accessed with a block of the second plane.

Abstract translation: 公开了一种3D存储器件，其包括具有形成在第一层上的第一垫的第一平面和形成在第一层上的第二层上的第三垫，第一和第三垫共享位线，第二平面具有 形成在第一层上的第二垫和形成在第二层上的第四垫。 第二和第四垫共享一点。 第一至第四垫中的每一个包括多个块，并且与第一平面相关联的块与第二平面的块同时访问。

公开(公告)号：US20100271893A1

公开(公告)日：2010-10-28

申请号：US12830465

申请日：2010-07-06

Applicant: Yeong-Taek Lee

Inventor： Yeong-Taek Lee

IPC: G11C7/06

CPC classification number: G11C11/404 ,  G11C11/4091 ,  G11C2211/4016

Abstract: A semiconductor memory device having a first memory cell array block including a memory cell having a floating body, the memory cell coupled to a word line, a first bit line, and a first source line, a second memory cell array block including a reference memory cell having a floating body, the reference memory cell coupled to a reference word line, a second bit line, and a second source line, a first isolation gate portion configured to selectively transmit a signal between the first bit line and at least one of a sense bit line and an inverted sense bit line, a second isolation gate portion configured to selectively transmit a signal between the second bit line and at least one of the sense bit lines, and a sense amplifier configured to amplify voltages of the sense bit line and the inverted sense bit line to first and second sense amplifying voltage levels.

Abstract translation: 一种具有第一存储单元阵列块的半导体存储器件，包括具有浮体的存储单元，耦合到字线的存储单元，第一位线和第一源极线，包括参考存储器的第二存储单元阵列块 具有浮体的单元，耦合到参考字线的参考存储单元，第二位线和第二源极线，第一隔离栅极部分，被配置为选择性地在第一位线和第一位线之间的信号 感测位线和反相感测位线，第二隔离栅极部分，被配置为选择性地在第二位线和感测位线中的至少一个之间传输信号;以及读出放大器，被配置为放大感测位线的电压， 反向感测位线到第一和第二感测放大电压电平。

公开(公告)号：US20100214819A1

公开(公告)日：2010-08-26

申请号：US12703354

申请日：2010-02-10

Applicant: Ho-Jung Kim ,  Yeong-Taek Lee ,  Chul-Woo Park ,  Sang-Beom Kang

Inventor： Ho-Jung Kim ,  Yeong-Taek Lee ,  Chul-Woo Park ,  Sang-Beom Kang

IPC: G11C11/00 ,  G11C5/14 ,  G11C7/00 ,  G11C7/02

CPC classification number: G11C13/004 ,  G11C8/10 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/005 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/009

Abstract: A resistive memory device includes a resistive memory cell array, an output circuit and an input circuit. The resistive memory cell array includes a plurality of memory cells that are coupled to bitlines. The output circuit generates a sensing output signal during a write operation by sensing a bitline voltage, and generates output data during a read operation by sensing the bitline voltage. The input circuit controls the bitline voltage based on input data for the write operation, and limits the bitline voltage in response to the sensing output signal during the write operation. The memory cells are protected by effectually limiting bitline voltage

Abstract translation: 电阻式存储器件包括电阻存储单元阵列，输出电路和输入电路。 电阻存储单元阵列包括耦合到位线的多个存储单元。 输出电路通过感测位线电压在写入操作期间产生感测输出信号，并通过感测位线电压在读取操作期间产生输出数据。 输入电路基于用于写入操作的输入数据来控制位线电压，并且在写入操作期间响应于感测输出信号来限制位线电压。 存储单元受到有效限制位线电压的保护

公开(公告)号：US07773427B2

公开(公告)日：2010-08-10

申请号：US12141737

申请日：2008-06-18

Applicant: Ki-Tae Park ,  Doo-Gon Kim ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Doo-Gon Kim ,  Yeong-Taek Lee

IPC: G11C11/34

CPC classification number: G11C16/3418

Abstract: A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage.

Abstract translation: 一种非易失性存储器件和操作方法，包括向多个存储器单元内的所选存储单元的栅极提供验证电压，并且在程序验证期间向存储器单元内的未选择存储单元的栅极提供第一通过电压 操作; 以及向所选择的存储单元的栅极提供读取电压，并且在读取操作期间向未选择的存储单元的栅极提供第二通过电压。 第二通过电压大于第一通过电压。

公开(公告)号：US20090290402A1

公开(公告)日：2009-11-26

申请号：US12453595

申请日：2009-05-15

Applicant: Ki-Whan Song ,  Yeong-Taek Lee

Inventor： Ki-Whan Song ,  Yeong-Taek Lee

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/06 ,  G11C8/08

CPC classification number: G11C7/18 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4097 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2211/4016 ,  G11C2213/79 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10891

Abstract: A semiconductor memory device and a method of arranging a memory cell array of the semiconductor device are provided. The semiconductor memory device has a memory cell array including a word line pair including a first word line and a second word line that are arranged in a first direction, a source line arranged in the first direction between the first word line and the second word line, a bit line pair including a first bit line and a second bit line arranged in a second direction perpendicular to the first direction, a first memory cell including a gate connected to the first word line and first and second regions respectively connected to the second bit line and the source line, and arranged in a third direction between the first direction and the second direction, and a second memory cell including a gate connected to the second word line, a third region and the second region respectively connected to the first bit line and the source line, and arranged in the third direction. The first word line and the second word line are simultaneously activated. Therefore, disturbance that may be generated between adjacent memory cells in the semiconductor memory cell can be prevented, integration density of the semiconductor memory device can be enhanced, and the number of word lines to be driven may be reduced to employ a sub-word line structure.

Abstract translation: 提供半导体存储器件和布置半导体器件的存储单元阵列的方法。 半导体存储器件具有存储单元阵列，该存储单元阵列包括包括沿第一方向布置的第一字线和第二字线的字线对，在第一字线和第二字线之间沿第一方向排列的源极线 ，包括沿与第一方向垂直的第二方向布置的第一位线和第二位线的位线对，包括连接到第一字线的栅极的第一存储器单元和分别连接到第二位线的第一和第二区域 线和源极线，并且在第一方向和第二方向之间沿第三方向布置，以及第二存储单元，其包括连接到第二字线的栅极，分别连接到第一位线的第三区域和第二区域 和源极线，并且布置在第三方向。 第一个字线和第二个字线同时被激活。 因此，可以防止在半导体存储单元中的相邻存储单元之间产生的干扰，可以提高半导体存储器件的集成密度，并且可以减少要驱动的字线的数量以使用子字线 结构体。

公开(公告)号：US07567452B2

公开(公告)日：2009-07-28

申请号：US11637519

申请日：2006-12-12

Applicant: Ki-whan Song ,  Yeong-taek Lee

Inventor： Ki-whan Song ,  Yeong-taek Lee

IPC: G11C11/02

CPC classification number: G11C11/24

Abstract: A multi-level dynamic memory device having an open bit line structure is disclosed. The multi-level dynamic memory device includes a plurality of word lines; a plurality of bit lines provided in an open bit line structure; a plurality of memory cells each of which is connected to each of the word lines and each of the bit lines and stores at least two bits of data; and a plurality of sense amplifiers, each of which amplifies a voltage difference between the bit lines, the bit lines being located at opposite sides of each of the plurality of sense amplifiers.

Abstract translation: 公开了一种具有开放位线结构的多级动态存储器件。 多级动态存储装置包括多个字线; 设置在开放位线结构中的多个位线; 多个存储单元，每个存储单元连接到每个字线和每个位线，并存储至少两位数据; 以及多个读出放大器，每个读出放大器放大位线之间的电压差，位线位于多个读出放大器的每一个的相对侧。

公开(公告)号：US07566927B2

公开(公告)日：2009-07-28

申请号：US10840580

申请日：2004-05-07

Applicant: Moo-Sung Kim ,  Yeong-Taek Lee ,  Seung-Jae Lee

Inventor： Moo-Sung Kim ,  Yeong-Taek Lee ,  Seung-Jae Lee

IPC: H01L29/788

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  H01L27/115

Abstract: A flash memory device may include a memory cell array having a plurality of word lines, bit lines, and memory cells. Each memory cell may be arranged at an intersection of a corresponding word line and a corresponding bit line. The device may include a bit line voltage setting circuit for setting a voltage on a bit line of a given memory cell to be programmed to a variable bit line voltage or to a ground voltage. A variable bit line voltage generating circuit may be provided in the flash memory device for generating the variable bit line voltage. To facilitating programming of the device, a bit line voltage of a given memory cell to be programmed may be set based on a supply voltage of the device, so as to maintain a voltage difference based on the set bit line voltage above a given threshold voltage.

Abstract translation: 闪存器件可以包括具有多个字线，位线和存储器单元的存储单元阵列。 每个存储单元可以被布置在对应的字线和对应的位线的交叉点处。 该设备可以包括位线电压设置电路，用于将要编程的给定存储器单元的位线上的电压设置为可变位线电压或接地电压。 可变位线电压产生电路可以设置在闪存器件中，用于产生可变位线电压。 为了便于设备的编程，可以基于设备的电源电压来设置要编程的给定存储器单元的位线电压，以便基于设定的位线电压维持高于给定阈值电压的电压差 。

公开(公告)号：US07542350B2

公开(公告)日：2009-06-02

申请号：US11616411

申请日：2006-12-27

Applicant: Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC: G11C16/04

CPC classification number: G11C16/349 ,  G11C16/3495

Abstract: Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages.

Abstract translation: 包括闪速存储器装置和用于控制闪速存储器件的存储器控​​制器的存储器系统中设置读取电压的方法包括顺序地改变分配读取电压以从闪速存储器装置读取页面数据; 构成具有数据位数和分布读电压的分布表，分别表示从闪存器件分别读取的页数据中的擦除状态的数据位数和与读页数据相对应的分布读电压; 基于分布表，检测对应于每个表示存储器单元的可能单元状态的最大点的数据位数的分布读取电压; 以及基于检测到的分布读取电压来定义新的读取电压。