METHODS AND APPARATUS FOR STABILIZING REFERENCE OSCILLATORS
    43.
    发明申请
    METHODS AND APPARATUS FOR STABILIZING REFERENCE OSCILLATORS 审中-公开
    用于稳定参考振荡器的方法和装置

    公开(公告)号:US20110212718A1

    公开(公告)日:2011-09-01

    申请号:US13036158

    申请日:2011-02-28

    IPC分类号: G01S19/46 H04B7/08 H04W4/00

    摘要: Apparatus and methods for stabilizing reference oscillators are described. According to some embodiments, the reference oscillator of a device may be stabilized by synchronizing the reference oscillator to an external signal received by the device. The device may be a navigation device in some embodiments, and the external signal may represent or be synchronized to an atomic clock signal or other signal exhibiting sufficient stability.

    摘要翻译: 描述用于稳定参考振荡器的装置和方法。 根据一些实施例,可以通过将参考振荡器与由器件接收的外部信号同步来使器件的参考振荡器稳定。 在一些实施例中,该设备可以是导航设备,并且外部信号可以表示或与原子钟信号或表现出足够稳定性的其它信号同步。

    Oscillators having arbitrary frequencies and related systems and methods
    46.
    发明授权
    Oscillators having arbitrary frequencies and related systems and methods 有权
    振荡器具有任意频率和相关的系统和方法

    公开(公告)号:US08896385B2

    公开(公告)日:2014-11-25

    申请号:US13410917

    申请日:2012-03-02

    CPC分类号: H03L7/06 H03L1/026 H03L7/16

    摘要: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

    摘要翻译: 描述了用于利用被配置为产生具有任意频率的振荡信号的振荡器进行操作的系统和方法。 振荡信号的频率可以通过将多个调谐信号或值施加到振荡器来移位以消除其任意性质。 或者,可以通过调整接收振荡信号的电路的一个或多个部件来调节任意频率。

    POWER-ON RESET CIRCUIT AND METHOD
    47.
    发明申请
    POWER-ON RESET CIRCUIT AND METHOD 有权
    上电复位电路和方法

    公开(公告)号:US20130106473A1

    公开(公告)日:2013-05-02

    申请号:US13281921

    申请日:2011-10-26

    IPC分类号: H03L7/00

    CPC分类号: H03L5/00 H03K17/223

    摘要: The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.

    摘要翻译: 所公开的上电复位电路提供电源电压Vdd何时以及是否达到触发电压电平Vtrig的指示。 所公开的电路包括触发器电路和第一比较器电路。 根据本发明的电路具有耦合到电源电压的触发器电路的D输入节点。 第一比较器电路输出时钟信号,其中触发电路由时钟信号计时。 触发电路的Q输出节点提供上电复位信号,当供电电压处于小于触发电压电平Vtrig的电压电平时,上电复位信号处于LO状态。 当电源电压处于大于触发电压电平Vtrig的电压电平时,上电复位信号处于HI状态。

    Power-on reset circuit and method
    48.
    发明授权
    Power-on reset circuit and method 有权
    上电复位电路及方法

    公开(公告)号:US08415993B1

    公开(公告)日:2013-04-09

    申请号:US13281921

    申请日:2011-10-26

    IPC分类号: H03L7/00

    CPC分类号: H03L5/00 H03K17/223

    摘要: The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.

    摘要翻译: 所公开的上电复位电路提供电源电压Vdd何时以及是否达到触发电压电平Vtrig的指示。 所公开的电路包括触发器电路和第一比较器电路。 根据本发明的电路具有耦合到电源电压的触发器电路的D输入节点。 第一比较器电路输出时钟信号,其中触发电路由时钟信号计时。 触发电路的Q输出节点提供上电复位信号,当供电电压处于小于触发电压电平Vtrig的电压电平时,上电复位信号处于LO状态。 当电源电压处于大于触发电压电平Vtrig的电压电平时,上电复位信号处于HI状态。

    Variable phase amplifier circuit and method of use
    50.
    发明授权
    Variable phase amplifier circuit and method of use 有权
    可变相位放大器电路及其使用方法

    公开(公告)号:US08395456B2

    公开(公告)日:2013-03-12

    申请号:US13049738

    申请日:2011-03-16

    IPC分类号: H03B5/30

    摘要: A variable phase amplifier circuit is disclosed and its method of use in tuning devices having resonators. The variable phase amplifier receives an input differential signal pair. The input differential signal pair can be generated by a resonator device. The variable phase amplifier generates a modified differential signal pair in response to receiving the input differential signal pair. The variable phase amplifier provides a means to vary the phase of the modified differential signal pair with respect to the input differential signal pair, in an accurate and stable manner. If the modified differential signal pair with a phase shift introduced in it is fed back to the resonator device, the resonator will change its frequency of oscillation, where the new frequency of oscillation is a function of the phase of the modified differential signal pair.

    摘要翻译: 公开了一种可变相位放大器电路及其在具有谐振器的调谐装置中的使用方法。 可变相位放大器接收输入差分信号对。 输入差分信号对可以由谐振器装置产生。 响应于接收到输入差分信号对,可变相位放大器产生修正的差分信号对。 可变相位放大器提供了以准确和稳定的方式改变修改的差分信号对相对于输入差分信号对的相位的装置。 如果将其中引入的相移的修正的差分信号对反馈到谐振器装置,则谐振器将改变其振荡频率,其中新的振荡频率是修改的差分信号对的相位的函数。